diff options
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/pinctrl-amd.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 281b700fe7e9..04ae139671c8 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -348,12 +348,21 @@ static void amd_gpio_irq_enable(struct irq_data *d) unsigned long flags; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); + u32 mask = BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF); raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + (d->hwirq)*4); pin_reg |= BIT(INTERRUPT_ENABLE_OFF); pin_reg |= BIT(INTERRUPT_MASK_OFF); writel(pin_reg, gpio_dev->base + (d->hwirq)*4); + /* + * When debounce logic is enabled it takes ~900 us before interrupts + * can be enabled. During this "debounce warm up" period the + * "INTERRUPT_ENABLE" bit will read as 0. Poll the bit here until it + * reads back as 1, signaling that interrupts are now enabled. + */ + while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) + continue; raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } |