summaryrefslogtreecommitdiffstats
path: root/include/linux/mfd
diff options
context:
space:
mode:
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/asic3.h185
-rw-r--r--include/linux/mfd/core.h55
-rw-r--r--include/linux/mfd/tc6393xb.h49
-rw-r--r--include/linux/mfd/tmio.h17
4 files changed, 216 insertions, 90 deletions
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h
index 4ab2162db13b..322cd6deb9f0 100644
--- a/include/linux/mfd/asic3.h
+++ b/include/linux/mfd/asic3.h
@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*
* Copyright 2001 Compaq Computer Corporation.
- * Copyright 2007 OpendHand.
+ * Copyright 2007-2008 OpenedHand Ltd.
*/
#ifndef __ASIC3_H__
@@ -16,43 +16,22 @@
#include <linux/types.h>
-struct asic3 {
- void __iomem *mapping;
- unsigned int bus_shift;
- unsigned int irq_nr;
- unsigned int irq_base;
- spinlock_t lock;
- u16 irq_bothedge[4];
- struct device *dev;
-};
-
struct asic3_platform_data {
- struct {
- u32 dir;
- u32 init;
- u32 sleep_mask;
- u32 sleep_out;
- u32 batt_fault_out;
- u32 sleep_conf;
- u32 alt_function;
- } gpio_a, gpio_b, gpio_c, gpio_d;
-
- unsigned int bus_shift;
+ u16 *gpio_config;
+ unsigned int gpio_config_num;
unsigned int irq_base;
- struct platform_device **children;
- unsigned int n_children;
+ unsigned int gpio_base;
};
-int asic3_gpio_get_value(struct asic3 *asic, unsigned gpio);
-void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
-
#define ASIC3_NUM_GPIO_BANKS 4
#define ASIC3_GPIOS_PER_BANK 16
#define ASIC3_NUM_GPIOS 64
#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
+#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
+
#define ASIC3_GPIO_BANK_A 0
#define ASIC3_GPIO_BANK_B 1
#define ASIC3_GPIO_BANK_C 2
@@ -64,32 +43,89 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
/* All offsets below are specified with this address bus shift */
#define ASIC3_DEFAULT_ADDR_SHIFT 2
-#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_Base + ASIC3_##base##_##reg)
+#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
#define ASIC3_GPIO_OFFSET(base, reg) \
- (ASIC3_GPIO_##base##_Base + ASIC3_GPIO_##reg)
-
-#define ASIC3_GPIO_A_Base 0x0000
-#define ASIC3_GPIO_B_Base 0x0100
-#define ASIC3_GPIO_C_Base 0x0200
-#define ASIC3_GPIO_D_Base 0x0300
-
-#define ASIC3_GPIO_Mask 0x00 /* R/W 0:don't mask */
-#define ASIC3_GPIO_Direction 0x04 /* R/W 0:input */
-#define ASIC3_GPIO_Out 0x08 /* R/W 0:output low */
-#define ASIC3_GPIO_TriggerType 0x0c /* R/W 0:level */
-#define ASIC3_GPIO_EdgeTrigger 0x10 /* R/W 0:falling */
-#define ASIC3_GPIO_LevelTrigger 0x14 /* R/W 0:low level detect */
-#define ASIC3_GPIO_SleepMask 0x18 /* R/W 0:don't mask in sleep mode */
-#define ASIC3_GPIO_SleepOut 0x1c /* R/W level 0:low in sleep mode */
-#define ASIC3_GPIO_BattFaultOut 0x20 /* R/W level 0:low in batt_fault */
-#define ASIC3_GPIO_IntStatus 0x24 /* R/W 0:none, 1:detect */
-#define ASIC3_GPIO_AltFunction 0x28 /* R/W 1:LED register control */
-#define ASIC3_GPIO_SleepConf 0x2c /*
+ (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
+
+#define ASIC3_GPIO_A_BASE 0x0000
+#define ASIC3_GPIO_B_BASE 0x0100
+#define ASIC3_GPIO_C_BASE 0x0200
+#define ASIC3_GPIO_D_BASE 0x0300
+
+#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
+#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \
+ (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
+#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
+#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
+#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
+
+#define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */
+#define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */
+#define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */
+#define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */
+#define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */
+#define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */
+#define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */
+#define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */
+#define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */
+#define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */
+#define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */
+#define ASIC3_GPIO_SLEEP_CONF 0x2c /*
* R/W bit 1: autosleep
* 0: disable gposlpout in normal mode,
* enable gposlpout in sleep mode.
*/
-#define ASIC3_GPIO_Status 0x30 /* R Pin status */
+#define ASIC3_GPIO_STATUS 0x30 /* R Pin status */
+
+/*
+ * ASIC3 GPIO config
+ *
+ * Bits 0..6 gpio number
+ * Bits 7..13 Alternate function
+ * Bit 14 Direction
+ * Bit 15 Initial value
+ *
+ */
+#define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
+#define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7)
+#define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14)
+#define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
+#define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
+ | (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
+ | (((init) & 0x1) << 15))
+#define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
+ ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
+#define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
+ ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
+
+/*
+ * Alternate functions
+ */
+#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0)
+#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0)
+#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0)
+#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 1, 0)
+#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 1, 0)
+#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 1, 0)
+#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0)
+#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0)
+#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0)
+#define ASIC3_GPIOC5_SPI_CLK ASIC3_CONFIG_GPIO(37, 1, 1, 0)
+#define ASIC3_GPIOC5_nCIOW ASIC3_CONFIG_GPIO(37, 1, 1, 0)
+#define ASIC3_GPIOC6_nCIOR ASIC3_CONFIG_GPIO(38, 1, 1, 0)
+#define ASIC3_GPIOC7_nPCE_1 ASIC3_CONFIG_GPIO(39, 1, 0, 0)
+#define ASIC3_GPIOC8_nPCE_2 ASIC3_CONFIG_GPIO(40, 1, 0, 0)
+#define ASIC3_GPIOC9_nPOE ASIC3_CONFIG_GPIO(41, 1, 0, 0)
+#define ASIC3_GPIOC10_nPWE ASIC3_CONFIG_GPIO(42, 1, 0, 0)
+#define ASIC3_GPIOC11_PSKTSEL ASIC3_CONFIG_GPIO(43, 1, 0, 0)
+#define ASIC3_GPIOC12_nPREG ASIC3_CONFIG_GPIO(44, 1, 0, 0)
+#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0)
+#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0)
+#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0)
+#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0)
+#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0)
+#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0)
+
#define ASIC3_SPI_Base 0x0400
#define ASIC3_SPI_Control 0x0000
@@ -128,7 +164,7 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
-#define ASIC3_CLOCK_Base 0x0A00
+#define ASIC3_CLOCK_BASE 0x0A00
#define ASIC3_CLOCK_CDEX 0x00
#define ASIC3_CLOCK_SEL 0x04
@@ -159,12 +195,12 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
#define CLOCK_SEL_CX (1 << 2)
-#define ASIC3_INTR_Base 0x0B00
+#define ASIC3_INTR_BASE 0x0B00
-#define ASIC3_INTR_IntMask 0x00 /* Interrupt mask control */
-#define ASIC3_INTR_PIntStat 0x04 /* Peripheral interrupt status */
-#define ASIC3_INTR_IntCPS 0x08 /* Interrupt timer clock pre-scale */
-#define ASIC3_INTR_IntTBS 0x0c /* Interrupt timer set */
+#define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */
+#define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */
+#define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */
+#define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */
#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */
@@ -227,44 +263,12 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
/*********************************************
- * The Onewire interface registers
- *
- * OWM_CMD
- * OWM_DAT
- * OWM_INTR
- * OWM_INTEN
- * OWM_CLKDIV
+ * The Onewire interface (DS1WM) is handled
+ * by the ds1wm driver.
*
*********************************************/
-#define ASIC3_OWM_Base 0xC00
-
-#define ASIC3_OWM_CMD 0x00
-#define ASIC3_OWM_DAT 0x04
-#define ASIC3_OWM_INTR 0x08
-#define ASIC3_OWM_INTEN 0x0C
-#define ASIC3_OWM_CLKDIV 0x10
-
-#define ASIC3_OWM_CMD_ONEWR (1 << 0)
-#define ASIC3_OWM_CMD_SRA (1 << 1)
-#define ASIC3_OWM_CMD_DQO (1 << 2)
-#define ASIC3_OWM_CMD_DQI (1 << 3)
-
-#define ASIC3_OWM_INTR_PD (1 << 0)
-#define ASIC3_OWM_INTR_PDR (1 << 1)
-#define ASIC3_OWM_INTR_TBE (1 << 2)
-#define ASIC3_OWM_INTR_TEMP (1 << 3)
-#define ASIC3_OWM_INTR_RBF (1 << 4)
-
-#define ASIC3_OWM_INTEN_EPD (1 << 0)
-#define ASIC3_OWM_INTEN_IAS (1 << 1)
-#define ASIC3_OWM_INTEN_ETBE (1 << 2)
-#define ASIC3_OWM_INTEN_ETMT (1 << 3)
-#define ASIC3_OWM_INTEN_ERBF (1 << 4)
-
-#define ASIC3_OWM_CLKDIV_PRE (3 << 0) /* two bits wide at bit 0 */
-#define ASIC3_OWM_CLKDIV_DIV (7 << 2) /* 3 bits wide at bit 2 */
-
+#define ASIC3_OWM_BASE 0xC00
/*****************************************************************************
* The SD configuration registers are at a completely different location
@@ -492,6 +496,7 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
#define ASIC3_SDIO_CTRL_LEDCtrl 0x7C
#define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0
-#define ASIC3_MAP_SIZE 0x2000
+#define ASIC3_MAP_SIZE_32BIT 0x2000
+#define ASIC3_MAP_SIZE_16BIT 0x1000
#endif /* __ASIC3_H__ */
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
new file mode 100644
index 000000000000..bb3dd0545928
--- /dev/null
+++ b/include/linux/mfd/core.h
@@ -0,0 +1,55 @@
+#ifndef MFD_CORE_H
+#define MFD_CORE_H
+/*
+ * drivers/mfd/mfd-core.h
+ *
+ * core MFD support
+ * Copyright (c) 2006 Ian Molton
+ * Copyright (c) 2007 Dmitry Baryshkov
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/platform_device.h>
+
+/*
+ * This struct describes the MFD part ("cell").
+ * After registration the copy of this structure will become the platform data
+ * of the resulting platform_device
+ */
+struct mfd_cell {
+ const char *name;
+
+ int (*enable)(struct platform_device *dev);
+ int (*disable)(struct platform_device *dev);
+ int (*suspend)(struct platform_device *dev);
+ int (*resume)(struct platform_device *dev);
+
+ void *driver_data; /* driver-specific data */
+
+ /*
+ * This resources can be specified relatievly to the parent device.
+ * For accessing device you should use resources from device
+ */
+ int num_resources;
+ const struct resource *resources;
+};
+
+static inline struct mfd_cell *
+mfd_get_cell(struct platform_device *pdev)
+{
+ return (struct mfd_cell *)pdev->dev.platform_data;
+}
+
+extern int mfd_add_devices(
+ struct platform_device *parent,
+ const struct mfd_cell *cells, int n_devs,
+ struct resource *mem_base,
+ int irq_base);
+
+extern void mfd_remove_devices(struct platform_device *parent);
+
+#endif
diff --git a/include/linux/mfd/tc6393xb.h b/include/linux/mfd/tc6393xb.h
new file mode 100644
index 000000000000..7cc824a58f7c
--- /dev/null
+++ b/include/linux/mfd/tc6393xb.h
@@ -0,0 +1,49 @@
+/*
+ * Toshiba TC6393XB SoC support
+ *
+ * Copyright(c) 2005-2006 Chris Humbert
+ * Copyright(c) 2005 Dirk Opfer
+ * Copyright(c) 2005 Ian Molton <spyro@f2s.com>
+ * Copyright(c) 2007 Dmitry Baryshkov
+ *
+ * Based on code written by Sharp/Lineo for 2.4 kernels
+ * Based on locomo.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef TC6393XB_H
+#define TC6393XB_H
+
+/* Also one should provide the CK3P6MI clock */
+struct tc6393xb_platform_data {
+ u16 scr_pll2cr; /* PLL2 Control */
+ u16 scr_gper; /* GP Enable */
+ u32 scr_gpo_doecr; /* GPO Data OE Control */
+ u32 scr_gpo_dsr; /* GPO Data Set */
+
+ int (*enable)(struct platform_device *dev);
+ int (*disable)(struct platform_device *dev);
+ int (*suspend)(struct platform_device *dev);
+ int (*resume)(struct platform_device *dev);
+
+ int irq_base; /* a base for cascaded irq */
+ int gpio_base;
+
+ struct tmio_nand_data *nand_data;
+};
+
+/*
+ * Relative to irq_base
+ */
+#define IRQ_TC6393_NAND 0
+#define IRQ_TC6393_MMC 1
+#define IRQ_TC6393_OHCI 2
+#define IRQ_TC6393_SERIAL 3
+#define IRQ_TC6393_FB 4
+
+#define TC6393XB_NR_IRQS 8
+
+#endif
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
new file mode 100644
index 000000000000..9438d8c9ac1c
--- /dev/null
+++ b/include/linux/mfd/tmio.h
@@ -0,0 +1,17 @@
+#ifndef MFD_TMIO_H
+#define MFD_TMIO_H
+
+/*
+ * data for the NAND controller
+ */
+struct tmio_nand_data {
+ struct nand_bbt_descr *badblock_pattern;
+ struct mtd_partition *partition;
+ unsigned int num_partitions;
+};
+
+#define TMIO_NAND_CONFIG "tmio-nand-config"
+#define TMIO_NAND_CONTROL "tmio-nand-control"
+#define TMIO_NAND_IRQ "tmio-nand"
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-15 23:09:37 +0000