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-rw-r--r--include/dt-bindings/interconnect/qcom,msm8974.h146
-rw-r--r--include/linux/coresight.h6
-rw-r--r--include/linux/firmware/intel/stratix10-svc-client.h8
-rw-r--r--include/linux/miscdevice.h1
-rw-r--r--include/linux/nvmem-consumer.h2
-rw-r--r--include/linux/parport.h1
-rw-r--r--include/linux/phy/phy.h3
-rw-r--r--include/linux/phy/tegra/xusb.h4
-rw-r--r--include/linux/rtsx_pci.h1
-rw-r--r--include/linux/soundwire/sdw.h7
-rw-r--r--include/linux/w1.h1
-rw-r--r--include/trace/events/fsi.h6
-rw-r--r--include/trace/events/fsi_master_aspeed.h77
-rw-r--r--include/uapi/misc/fastrpc.h15
-rw-r--r--include/uapi/misc/habanalabs.h48
15 files changed, 306 insertions, 20 deletions
diff --git a/include/dt-bindings/interconnect/qcom,msm8974.h b/include/dt-bindings/interconnect/qcom,msm8974.h
new file mode 100644
index 000000000000..e65ae27ffff2
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,msm8974.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
+/*
+ * Qualcomm msm8974 interconnect IDs
+ *
+ * Copyright (c) 2019 Brian Masney <masneyb@onstation.org>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H
+
+#define BIMC_MAS_AMPSS_M0 0
+#define BIMC_MAS_AMPSS_M1 1
+#define BIMC_MAS_MSS_PROC 2
+#define BIMC_TO_MNOC 3
+#define BIMC_TO_SNOC 4
+#define BIMC_SLV_EBI_CH0 5
+#define BIMC_SLV_AMPSS_L2 6
+
+#define CNOC_MAS_RPM_INST 0
+#define CNOC_MAS_RPM_DATA 1
+#define CNOC_MAS_RPM_SYS 2
+#define CNOC_MAS_DEHR 3
+#define CNOC_MAS_QDSS_DAP 4
+#define CNOC_MAS_SPDM 5
+#define CNOC_MAS_TIC 6
+#define CNOC_SLV_CLK_CTL 7
+#define CNOC_SLV_CNOC_MSS 8
+#define CNOC_SLV_SECURITY 9
+#define CNOC_SLV_TCSR 10
+#define CNOC_SLV_TLMM 11
+#define CNOC_SLV_CRYPTO_0_CFG 12
+#define CNOC_SLV_CRYPTO_1_CFG 13
+#define CNOC_SLV_IMEM_CFG 14
+#define CNOC_SLV_MESSAGE_RAM 15
+#define CNOC_SLV_BIMC_CFG 16
+#define CNOC_SLV_BOOT_ROM 17
+#define CNOC_SLV_PMIC_ARB 18
+#define CNOC_SLV_SPDM_WRAPPER 19
+#define CNOC_SLV_DEHR_CFG 20
+#define CNOC_SLV_MPM 21
+#define CNOC_SLV_QDSS_CFG 22
+#define CNOC_SLV_RBCPR_CFG 23
+#define CNOC_SLV_RBCPR_QDSS_APU_CFG 24
+#define CNOC_TO_SNOC 25
+#define CNOC_SLV_CNOC_ONOC_CFG 26
+#define CNOC_SLV_CNOC_MNOC_MMSS_CFG 27
+#define CNOC_SLV_CNOC_MNOC_CFG 28
+#define CNOC_SLV_PNOC_CFG 29
+#define CNOC_SLV_SNOC_MPU_CFG 30
+#define CNOC_SLV_SNOC_CFG 31
+#define CNOC_SLV_EBI1_DLL_CFG 32
+#define CNOC_SLV_PHY_APU_CFG 33
+#define CNOC_SLV_EBI1_PHY_CFG 34
+#define CNOC_SLV_RPM 35
+#define CNOC_SLV_SERVICE_CNOC 36
+
+#define MNOC_MAS_GRAPHICS_3D 0
+#define MNOC_MAS_JPEG 1
+#define MNOC_MAS_MDP_PORT0 2
+#define MNOC_MAS_VIDEO_P0 3
+#define MNOC_MAS_VIDEO_P1 4
+#define MNOC_MAS_VFE 5
+#define MNOC_TO_CNOC 6
+#define MNOC_TO_BIMC 7
+#define MNOC_SLV_CAMERA_CFG 8
+#define MNOC_SLV_DISPLAY_CFG 9
+#define MNOC_SLV_OCMEM_CFG 10
+#define MNOC_SLV_CPR_CFG 11
+#define MNOC_SLV_CPR_XPU_CFG 12
+#define MNOC_SLV_MISC_CFG 13
+#define MNOC_SLV_MISC_XPU_CFG 14
+#define MNOC_SLV_VENUS_CFG 15
+#define MNOC_SLV_GRAPHICS_3D_CFG 16
+#define MNOC_SLV_MMSS_CLK_CFG 17
+#define MNOC_SLV_MMSS_CLK_XPU_CFG 18
+#define MNOC_SLV_MNOC_MPU_CFG 19
+#define MNOC_SLV_ONOC_MPU_CFG 20
+#define MNOC_SLV_SERVICE_MNOC 21
+
+#define OCMEM_NOC_TO_OCMEM_VNOC 0
+#define OCMEM_MAS_JPEG_OCMEM 1
+#define OCMEM_MAS_MDP_OCMEM 2
+#define OCMEM_MAS_VIDEO_P0_OCMEM 3
+#define OCMEM_MAS_VIDEO_P1_OCMEM 4
+#define OCMEM_MAS_VFE_OCMEM 5
+#define OCMEM_MAS_CNOC_ONOC_CFG 6
+#define OCMEM_SLV_SERVICE_ONOC 7
+#define OCMEM_VNOC_TO_SNOC 8
+#define OCMEM_VNOC_TO_OCMEM_NOC 9
+#define OCMEM_VNOC_MAS_GFX3D 10
+#define OCMEM_SLV_OCMEM 11
+
+#define PNOC_MAS_PNOC_CFG 0
+#define PNOC_MAS_SDCC_1 1
+#define PNOC_MAS_SDCC_3 2
+#define PNOC_MAS_SDCC_4 3
+#define PNOC_MAS_SDCC_2 4
+#define PNOC_MAS_TSIF 5
+#define PNOC_MAS_BAM_DMA 6
+#define PNOC_MAS_BLSP_2 7
+#define PNOC_MAS_USB_HSIC 8
+#define PNOC_MAS_BLSP_1 9
+#define PNOC_MAS_USB_HS 10
+#define PNOC_TO_SNOC 11
+#define PNOC_SLV_SDCC_1 12
+#define PNOC_SLV_SDCC_3 13
+#define PNOC_SLV_SDCC_2 14
+#define PNOC_SLV_SDCC_4 15
+#define PNOC_SLV_TSIF 16
+#define PNOC_SLV_BAM_DMA 17
+#define PNOC_SLV_BLSP_2 18
+#define PNOC_SLV_USB_HSIC 19
+#define PNOC_SLV_BLSP_1 20
+#define PNOC_SLV_USB_HS 21
+#define PNOC_SLV_PDM 22
+#define PNOC_SLV_PERIPH_APU_CFG 23
+#define PNOC_SLV_PNOC_MPU_CFG 24
+#define PNOC_SLV_PRNG 25
+#define PNOC_SLV_SERVICE_PNOC 26
+
+#define SNOC_MAS_LPASS_AHB 0
+#define SNOC_MAS_QDSS_BAM 1
+#define SNOC_MAS_SNOC_CFG 2
+#define SNOC_TO_BIMC 3
+#define SNOC_TO_CNOC 4
+#define SNOC_TO_PNOC 5
+#define SNOC_TO_OCMEM_VNOC 6
+#define SNOC_MAS_CRYPTO_CORE0 7
+#define SNOC_MAS_CRYPTO_CORE1 8
+#define SNOC_MAS_LPASS_PROC 9
+#define SNOC_MAS_MSS 10
+#define SNOC_MAS_MSS_NAV 11
+#define SNOC_MAS_OCMEM_DMA 12
+#define SNOC_MAS_WCSS 13
+#define SNOC_MAS_QDSS_ETR 14
+#define SNOC_MAS_USB3 15
+#define SNOC_SLV_AMPSS 16
+#define SNOC_SLV_LPASS 17
+#define SNOC_SLV_USB3 18
+#define SNOC_SLV_WCSS 19
+#define SNOC_SLV_OCIMEM 20
+#define SNOC_SLV_SNOC_OCMEM 21
+#define SNOC_SLV_SERVICE_SNOC 22
+#define SNOC_SLV_QDSS_STM 23
+
+#endif
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index a2b68823717b..44e552de419c 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -285,6 +285,8 @@ extern void coresight_disclaim_device(void __iomem *base);
extern void coresight_disclaim_device_unlocked(void __iomem *base);
extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
struct device *dev);
+
+extern bool coresight_loses_context_with_cpu(struct device *dev);
#else
static inline struct coresight_device *
coresight_register(struct coresight_desc *desc) { return NULL; }
@@ -307,6 +309,10 @@ static inline int coresight_claim_device(void __iomem *base)
static inline void coresight_disclaim_device(void __iomem *base) {}
static inline void coresight_disclaim_device_unlocked(void __iomem *base) {}
+static inline bool coresight_loses_context_with_cpu(struct device *dev)
+{
+ return false;
+}
#endif
extern int coresight_get_cpu(struct device *dev);
diff --git a/include/linux/firmware/intel/stratix10-svc-client.h b/include/linux/firmware/intel/stratix10-svc-client.h
index b6c4302a39e0..59bc6e2af693 100644
--- a/include/linux/firmware/intel/stratix10-svc-client.h
+++ b/include/linux/firmware/intel/stratix10-svc-client.h
@@ -41,6 +41,12 @@
*
* SVC_STATUS_RSU_OK:
* Secure firmware accepts the request of remote status update (RSU).
+ *
+ * SVC_STATUS_RSU_ERROR:
+ * Error encountered during remote system update.
+ *
+ * SVC_STATUS_RSU_NO_SUPPORT:
+ * Secure firmware doesn't support RSU retry or notify feature.
*/
#define SVC_STATUS_RECONFIG_REQUEST_OK 0
#define SVC_STATUS_RECONFIG_BUFFER_SUBMITTED 1
@@ -50,6 +56,8 @@
#define SVC_STATUS_RECONFIG_ERROR 5
#define SVC_STATUS_RSU_OK 6
#define SVC_STATUS_RSU_ERROR 7
+#define SVC_STATUS_RSU_NO_SUPPORT 8
+
/**
* Flag bit for COMMAND_RECONFIG
*
diff --git a/include/linux/miscdevice.h b/include/linux/miscdevice.h
index 3247a3dc7934..b06b75776a32 100644
--- a/include/linux/miscdevice.h
+++ b/include/linux/miscdevice.h
@@ -57,6 +57,7 @@
#define UHID_MINOR 239
#define USERIO_MINOR 240
#define VHOST_VSOCK_MINOR 241
+#define RFKILL_MINOR 242
#define MISC_DYNAMIC_MINOR 255
struct device;
diff --git a/include/linux/nvmem-consumer.h b/include/linux/nvmem-consumer.h
index 02dc4aa992b2..d3776be48c53 100644
--- a/include/linux/nvmem-consumer.h
+++ b/include/linux/nvmem-consumer.h
@@ -121,7 +121,7 @@ static inline void *nvmem_cell_read(struct nvmem_cell *cell, size_t *len)
}
static inline int nvmem_cell_write(struct nvmem_cell *cell,
- const char *buf, size_t len)
+ void *buf, size_t len)
{
return -EOPNOTSUPP;
}
diff --git a/include/linux/parport.h b/include/linux/parport.h
index 397607a0c0eb..13932ce8b37b 100644
--- a/include/linux/parport.h
+++ b/include/linux/parport.h
@@ -460,6 +460,7 @@ extern size_t parport_ieee1284_epp_read_addr (struct parport *,
void *, size_t, int);
/* IEEE1284.3 functions */
+#define daisy_dev_name "Device ID probe"
extern int parport_daisy_init (struct parport *port);
extern void parport_daisy_fini (struct parport *port);
extern struct pardevice *parport_open (int devnum, const char *name);
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 15032f145063..56d3a100006a 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -38,7 +38,8 @@ enum phy_mode {
PHY_MODE_PCIE,
PHY_MODE_ETHERNET,
PHY_MODE_MIPI_DPHY,
- PHY_MODE_SATA
+ PHY_MODE_SATA,
+ PHY_MODE_LVDS,
};
/**
diff --git a/include/linux/phy/tegra/xusb.h b/include/linux/phy/tegra/xusb.h
index ee59562c8354..1235865e7e2c 100644
--- a/include/linux/phy/tegra/xusb.h
+++ b/include/linux/phy/tegra/xusb.h
@@ -18,5 +18,7 @@ int tegra_xusb_padctl_hsic_set_idle(struct tegra_xusb_padctl *padctl,
unsigned int port, bool idle);
int tegra_xusb_padctl_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl,
unsigned int port, bool enable);
-
+int tegra_xusb_padctl_set_vbus_override(struct tegra_xusb_padctl *padctl,
+ bool val);
+int tegra_phy_xusb_utmi_port_reset(struct phy *phy);
#endif /* PHY_TEGRA_XUSB_H */
diff --git a/include/linux/rtsx_pci.h b/include/linux/rtsx_pci.h
index f87da30a58b1..65b8142a7fed 100644
--- a/include/linux/rtsx_pci.h
+++ b/include/linux/rtsx_pci.h
@@ -1262,6 +1262,7 @@ struct rtsx_pcr {
#define PID_5250 0x5250
#define PID_525A 0x525A
#define PID_5260 0x5260
+#define PID_5261 0x5261
#define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
#define PCI_VID(pcr) ((pcr)->pci->vendor)
diff --git a/include/linux/soundwire/sdw.h b/include/linux/soundwire/sdw.h
index ea787201c3ac..28745b9ba279 100644
--- a/include/linux/soundwire/sdw.h
+++ b/include/linux/soundwire/sdw.h
@@ -40,9 +40,6 @@ struct sdw_slave;
#define SDW_VALID_PORT_RANGE(n) ((n) <= 14 && (n) >= 1)
-#define SDW_DAI_ID_RANGE_START 100
-#define SDW_DAI_ID_RANGE_END 200
-
enum {
SDW_PORT_DIRN_SINK = 0,
SDW_PORT_DIRN_SOURCE,
@@ -406,6 +403,8 @@ int sdw_slave_read_prop(struct sdw_slave *slave);
* SDW Slave Structures and APIs
*/
+#define SDW_IGNORED_UNIQUE_ID 0xFF
+
/**
* struct sdw_slave_id - Slave ID
* @mfg_id: MIPI Manufacturer ID
@@ -421,7 +420,7 @@ struct sdw_slave_id {
__u16 mfg_id;
__u16 part_id;
__u8 class_id;
- __u8 unique_id:4;
+ __u8 unique_id;
__u8 sdw_version:4;
};
diff --git a/include/linux/w1.h b/include/linux/w1.h
index 7da0c7588e04..cebf3464bc03 100644
--- a/include/linux/w1.h
+++ b/include/linux/w1.h
@@ -262,6 +262,7 @@ struct w1_family_ops {
* @family_entry: family linked list
* @fid: 8 bit family identifier
* @fops: operations for this family
+ * @of_match_table: open firmware match table
* @refcnt: reference counter
*/
struct w1_family {
diff --git a/include/trace/events/fsi.h b/include/trace/events/fsi.h
index 92e5e89e52ed..9832cb8e0eb0 100644
--- a/include/trace/events/fsi.h
+++ b/include/trace/events/fsi.h
@@ -26,7 +26,7 @@ TRACE_EVENT(fsi_master_read,
__entry->addr = addr;
__entry->size = size;
),
- TP_printk("fsi%d:%02d:%02d %08x[%zd]",
+ TP_printk("fsi%d:%02d:%02d %08x[%zu]",
__entry->master_idx,
__entry->link,
__entry->id,
@@ -56,7 +56,7 @@ TRACE_EVENT(fsi_master_write,
__entry->data = 0;
memcpy(&__entry->data, data, size);
),
- TP_printk("fsi%d:%02d:%02d %08x[%zd] <= {%*ph}",
+ TP_printk("fsi%d:%02d:%02d %08x[%zu] <= {%*ph}",
__entry->master_idx,
__entry->link,
__entry->id,
@@ -93,7 +93,7 @@ TRACE_EVENT(fsi_master_rw_result,
if (__entry->write || !__entry->ret)
memcpy(&__entry->data, data, size);
),
- TP_printk("fsi%d:%02d:%02d %08x[%zd] %s {%*ph} ret %d",
+ TP_printk("fsi%d:%02d:%02d %08x[%zu] %s {%*ph} ret %d",
__entry->master_idx,
__entry->link,
__entry->id,
diff --git a/include/trace/events/fsi_master_aspeed.h b/include/trace/events/fsi_master_aspeed.h
new file mode 100644
index 000000000000..a355ceacc33f
--- /dev/null
+++ b/include/trace/events/fsi_master_aspeed.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM fsi_master_aspeed
+
+#if !defined(_TRACE_FSI_MASTER_ASPEED_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_FSI_MASTER_ASPEED_H
+
+#include <linux/tracepoint.h>
+
+TRACE_EVENT(fsi_master_aspeed_opb_read,
+ TP_PROTO(uint32_t addr, size_t size, uint32_t result, uint32_t status, uint32_t irq_status),
+ TP_ARGS(addr, size, result, status, irq_status),
+ TP_STRUCT__entry(
+ __field(uint32_t, addr)
+ __field(size_t, size)
+ __field(uint32_t, result)
+ __field(uint32_t, status)
+ __field(uint32_t, irq_status)
+ ),
+ TP_fast_assign(
+ __entry->addr = addr;
+ __entry->size = size;
+ __entry->result = result;
+ __entry->status = status;
+ __entry->irq_status = irq_status;
+ ),
+ TP_printk("addr %08x size %zu: result %08x sts: %08x irq_sts: %08x",
+ __entry->addr, __entry->size, __entry->result,
+ __entry->status, __entry->irq_status
+ )
+);
+
+TRACE_EVENT(fsi_master_aspeed_opb_write,
+ TP_PROTO(uint32_t addr, uint32_t val, size_t size, uint32_t status, uint32_t irq_status),
+ TP_ARGS(addr, val, size, status, irq_status),
+ TP_STRUCT__entry(
+ __field(uint32_t, addr)
+ __field(uint32_t, val)
+ __field(size_t, size)
+ __field(uint32_t, status)
+ __field(uint32_t, irq_status)
+ ),
+ TP_fast_assign(
+ __entry->addr = addr;
+ __entry->val = val;
+ __entry->size = size;
+ __entry->status = status;
+ __entry->irq_status = irq_status;
+ ),
+ TP_printk("addr %08x val %08x size %zu status: %08x irq_sts: %08x",
+ __entry->addr, __entry->val, __entry->size,
+ __entry->status, __entry->irq_status
+ )
+ );
+
+TRACE_EVENT(fsi_master_aspeed_opb_error,
+ TP_PROTO(uint32_t mresp0, uint32_t mstap0, uint32_t mesrb0),
+ TP_ARGS(mresp0, mstap0, mesrb0),
+ TP_STRUCT__entry(
+ __field(uint32_t, mresp0)
+ __field(uint32_t, mstap0)
+ __field(uint32_t, mesrb0)
+ ),
+ TP_fast_assign(
+ __entry->mresp0 = mresp0;
+ __entry->mstap0 = mstap0;
+ __entry->mesrb0 = mesrb0;
+ ),
+ TP_printk("mresp0 %08x mstap0 %08x mesrb0 %08x",
+ __entry->mresp0, __entry->mstap0, __entry->mesrb0
+ )
+ );
+
+#endif
+
+#include <trace/define_trace.h>
diff --git a/include/uapi/misc/fastrpc.h b/include/uapi/misc/fastrpc.h
index fb792e882cef..07de2b7aac85 100644
--- a/include/uapi/misc/fastrpc.h
+++ b/include/uapi/misc/fastrpc.h
@@ -10,6 +10,8 @@
#define FASTRPC_IOCTL_INVOKE _IOWR('R', 3, struct fastrpc_invoke)
#define FASTRPC_IOCTL_INIT_ATTACH _IO('R', 4)
#define FASTRPC_IOCTL_INIT_CREATE _IOWR('R', 5, struct fastrpc_init_create)
+#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct fastrpc_req_mmap)
+#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 7, struct fastrpc_req_munmap)
struct fastrpc_invoke_args {
__u64 ptr;
@@ -38,4 +40,17 @@ struct fastrpc_alloc_dma_buf {
__u64 size; /* size */
};
+struct fastrpc_req_mmap {
+ __s32 fd;
+ __u32 flags; /* flags for dsp to map with */
+ __u64 vaddrin; /* optional virtual address */
+ __u64 size; /* size */
+ __u64 vaddrout; /* dsp virtual address */
+};
+
+struct fastrpc_req_munmap {
+ __u64 vaddrout; /* address to unmap */
+ __u64 size; /* size */
+};
+
#endif /* __QCOM_FASTRPC_H__ */
diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h
index 39c4ea51a719..4faa2c9767e5 100644
--- a/include/uapi/misc/habanalabs.h
+++ b/include/uapi/misc/habanalabs.h
@@ -88,13 +88,19 @@ enum hl_device_status {
* internal engine.
* HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't
* require an open context.
- * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device
- * over the last period specified by the user.
- * The period can be between 100ms to 1s, in
- * resolution of 100ms. The return value is a
- * percentage of the utilization rate.
+ * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device
+ * over the last period specified by the user.
+ * The period can be between 100ms to 1s, in
+ * resolution of 100ms. The return value is a
+ * percentage of the utilization rate.
* HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each
* event occurred since the driver was loaded.
+ * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate
+ * of the device in MHz. The maximum clock rate is
+ * configurable via sysfs parameter
+ * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset
+ * operations performed on the device since the last
+ * time the driver was loaded.
*/
#define HL_INFO_HW_IP_INFO 0
#define HL_INFO_HW_EVENTS 1
@@ -103,8 +109,11 @@ enum hl_device_status {
#define HL_INFO_DEVICE_STATUS 4
#define HL_INFO_DEVICE_UTILIZATION 6
#define HL_INFO_HW_EVENTS_AGGREGATE 7
+#define HL_INFO_CLK_RATE 8
+#define HL_INFO_RESET_COUNT 9
#define HL_INFO_VERSION_MAX_LEN 128
+#define HL_INFO_CARD_NAME_MAX_LEN 16
struct hl_info_hw_ip_info {
__u64 sram_base_address;
@@ -123,6 +132,7 @@ struct hl_info_hw_ip_info {
__u8 dram_enabled;
__u8 pad[2];
__u8 armcp_version[HL_INFO_VERSION_MAX_LEN];
+ __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN];
};
struct hl_info_dram_usage {
@@ -149,6 +159,16 @@ struct hl_info_device_utilization {
__u32 pad;
};
+struct hl_info_clk_rate {
+ __u32 cur_clk_rate_mhz;
+ __u32 max_clk_rate_mhz;
+};
+
+struct hl_info_reset_count {
+ __u32 hard_reset_cnt;
+ __u32 soft_reset_cnt;
+};
+
struct hl_info_args {
/* Location of relevant struct in userspace */
__u64 return_pointer;
@@ -181,13 +201,15 @@ struct hl_info_args {
/* Opcode to destroy previously created command buffer */
#define HL_CB_OP_DESTROY 1
+#define HL_MAX_CB_SIZE 0x200000 /* 2MB */
+
struct hl_cb_in {
/* Handle of CB or 0 if we want to create one */
__u64 cb_handle;
/* HL_CB_OP_* */
__u32 op;
- /* Size of CB. Maximum size is 2MB. The minimum size that will be
- * allocated, regardless of this parameter's value, is PAGE_SIZE
+ /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that
+ * will be allocated, regardless of this parameter's value, is PAGE_SIZE
*/
__u32 cb_size;
/* Context ID - Currently not in use */
@@ -233,6 +255,8 @@ struct hl_cs_chunk {
#define HL_CS_STATUS_SUCCESS 0
+#define HL_MAX_JOBS_PER_CS 512
+
struct hl_cs_in {
/* this holds address of array of hl_cs_chunk for restore phase */
__u64 chunks_restore;
@@ -242,9 +266,13 @@ struct hl_cs_in {
* Currently not in use
*/
__u64 chunks_store;
- /* Number of chunks in restore phase array */
+ /* Number of chunks in restore phase array. Maximum number is
+ * HL_MAX_JOBS_PER_CS
+ */
__u32 num_chunks_restore;
- /* Number of chunks in execution array */
+ /* Number of chunks in execution array. Maximum number is
+ * HL_MAX_JOBS_PER_CS
+ */
__u32 num_chunks_execute;
/* Number of chunks in restore phase array - Currently not in use */
__u32 num_chunks_store;
@@ -589,7 +617,7 @@ struct hl_debug_args {
*
* The user can call this IOCTL with a handle it received from the CS IOCTL
* to wait until the handle's CS has finished executing. The user will wait
- * inside the kernel until the CS has finished or until the user-requeusted
+ * inside the kernel until the CS has finished or until the user-requested
* timeout has expired.
*
* The return value of the IOCTL is a standard Linux error code. The possible
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 20:25:23 +0000