diff options
Diffstat (limited to 'sound/soc/codecs/lpass-tx-macro.c')
| -rw-r--r-- | sound/soc/codecs/lpass-tx-macro.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c index 124c2e144f33..7e51212d4503 100644 --- a/sound/soc/codecs/lpass-tx-macro.c +++ b/sound/soc/codecs/lpass-tx-macro.c @@ -38,6 +38,8 @@ #define CDC_TX_TOP_CSR_I2S_RESET (0x00AC) #define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4) #define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0) +/* Default divider for AMIC and DMIC clock: DIV2 */ +#define CDC_TX_SWR_MIC_CLK_DEFAULT 0 #define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1) #define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4) #define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8) @@ -270,7 +272,6 @@ struct tx_macro { struct clk_hw hw; bool dec_active[NUM_DECIMATORS]; int tx_mclk_users; - u16 dmic_clk_div; bool bcs_enable; int dec_mode[NUM_DECIMATORS]; struct lpass_macro *pds; @@ -431,6 +432,8 @@ static bool tx_is_volatile_register(struct device *dev, unsigned int reg) case CDC_TX_TOP_CSR_SWR_DMIC1_CTL: case CDC_TX_TOP_CSR_SWR_DMIC2_CTL: case CDC_TX_TOP_CSR_SWR_DMIC3_CTL: + case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: + case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: return true; } return false; @@ -743,7 +746,6 @@ static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol, unsigned int val, dmic; u16 mic_sel_reg; u16 dmic_clk_reg; - struct tx_macro *tx = snd_soc_component_get_drvdata(component); val = ucontrol->value.enumerated.item[0]; if (val >= e->items) @@ -793,7 +795,7 @@ static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol, dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); snd_soc_component_write_field(component, dmic_clk_reg, CDC_TX_SWR_DMIC_CLK_SEL_MASK, - tx->dmic_clk_div); + CDC_TX_SWR_MIC_CLK_DEFAULT); } } @@ -882,7 +884,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, snd_soc_component_write_field(component, dmic_clk_reg, CDC_TX_SWR_DMIC_CLK_SEL_MASK, - tx->dmic_clk_div); + CDC_TX_SWR_MIC_CLK_DEFAULT); } } snd_soc_component_write_field(component, dec_cfg_reg, @@ -1848,8 +1850,10 @@ static int tx_macro_component_probe(struct snd_soc_component *comp) snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F, 0x0A); /* Enable swr mic0 and mic1 clock */ - snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00); - snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00); + snd_soc_component_write(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, + CDC_TX_SWR_MIC_CLK_DEFAULT); + snd_soc_component_write(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, + CDC_TX_SWR_MIC_CLK_DEFAULT); return 0; } |