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* Merge tag 'sunxi-clk-for-4.11' of ↵Stephen Boyd2017-02-0346-1332/+4877
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock updates from Maxime Ripard: - Support for one new SoC, the V3s - Conversion of two old SoCs to the new framework, the old sun5i family and the A80 - A bunch of fixes * tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits) ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU clk: sunxi-ng: Call divider_round_rate if we only have a single parent ARM: gr8: Convert to CCU ARM: sun5i: Convert to CCU clk: sunxi-ng: Add sun5i CCU driver clk: sunxi-ng: Implement global pre-divider clk: sunxi-ng: Implement multiplier maximum clk: sunxi-ng: mult: Fix minimum in round rate clk: sunxi-ng: Implement factors offsets clk: sunxi-ng: multiplier: Add fractional support clk: sunxi-ng: add support for V3s CCU dt-bindings: add device binding for the CCU of Allwinner V3s ...
| * ARM: dts: sun9i: Switch to new clock bindingsChen-Yu Tsai2017-01-301-297/+107
| | | | | | | | | | | | | | Now that we have a full clock driver for sun9i, switch to it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: Add A80 Display Engine CCUChen-Yu Tsai2017-01-306-0/+483
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the A80 SoC, Allwinner grouped and moved some subsystem specific clock controls to a separate address space, and possibly separate hardware block. One such subsystem is the display engine. The main clock control unit now only has 1 set of bus gate, dram gate, module clock, and reset control for the entire display subsystem. These feed into a secondary clock control unit, which has controls for each individual module of the display pipeline. This block is not documented in the user manual. Allwinner's kernel was used as the reference. Add support for the display engine clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: Add A80 USB CCUChen-Yu Tsai2017-01-306-0/+309
| | | | | | | | | | | | | | | | Add support for the USB clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: Add A80 CCUChen-Yu Tsai2017-01-307-0/+1556
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the main clock unit found in the A80. Some clocks were not documented in the released user manual, but were found in the official kernel from Allwinner. These include controls for the I2S, SPDIF, SATA, and eDP blocks. Note that on the A80, some subsystems have separate clock controllers downstream of the main clock unit. These include the MMC, USB, and display engine subsystems. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: Support separately grouped PLL lock status registerChen-Yu Tsai2017-01-302-2/+9
| | | | | | | | | | | | | | | | | | | | | | On the Allwinner A80 SoC, the PLL lock status indicators are grouped together in a separate register, as opposed to being scattered in each PLL's configuration register. Add a flag to support this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENTChen-Yu Tsai2017-01-301-1/+12
| | | | | | | | | | | | | | | | If the CLK_SET_RATE_PARENT flag is set, we want to try getting the closest parent rate. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flagChen-Yu Tsai2017-01-301-0/+15
| | | | | | | | | | | | | | | | | | This patch adds support for the CLK_SET_RATE_NO_REPARENT flag to the mux determine_rate helper, based on examples from clk-composite and clk-mux. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividersChen-Yu Tsai2017-01-301-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The determine_rate helper used ccu_mux_helper_adjust_parent_for_prediv() to adjust the parent_rate to account for pre-dividers, but then passed the pristine parent clock rate from clk_hw_get_rate() to the round() callback, thereby ignoring the pre-divider adjustment. In addition, it was saving the adjusted parent rate back into struct clk_rate_request. This patch fixes this by saving the pristine parent clock rate, and adding a copy that is adjusted and passed to the round() callback. The pristine copy, if it is the best solution, would be saved back to struct clk_rate_request. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPUMaxime Ripard2017-01-271-1/+1
| | | | | | | | | | | | | | | | | | In order to achieve all the rates asked by the GPU, we might need to change the parent frequency. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
| * clk: sunxi-ng: Call divider_round_rate if we only have a single parentMaxime Ripard2017-01-271-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | The divider_get_val function that is used in our determine_rate callback doesn't try to change the parent rate at all, while clk_divider_bestdiv, used in divider_round_rate, does. If we have a single parent, call divider_round_rate. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
| * ARM: gr8: Convert to CCUMaxime Ripard2017-01-231-464/+56
| | | | | | | | | | | | | | Now that we have a driver for the GR8, we can convert our DT to it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: sun5i: Convert to CCUMaxime Ripard2017-01-234-513/+75
| | | | | | | | | | | | | | | | Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: Add sun5i CCU driverMaxime Ripard2017-01-236-0/+1235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same silicon, and all share the same clocks. However, they're not packaged in the same way, and therefore not all the controllers are actually available on all these SoCs. Introduce a clock controller driver for all these SoCs with different compatibles to take that into account. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: Implement global pre-dividerMaxime Ripard2017-01-232-1/+9
| | | | | | | | | | | | | | | | | | | | | | Some clocks have a global pre-divider that applies to all their parents. Since it might also apply to clocks that have a single parent, this is merged in the ccu_common structure, unlike the other pre-divider settings that are tied to a specific index, and thus a specific parent. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: Implement multiplier maximumMaxime Ripard2017-01-236-20/+32
| | | | | | | | | | | | | | | | | | Some multipliers have a maximum rate that is lower than what the register width allows to. Add a field in the multiplier structure to allow CCU driver to set that maximum. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: mult: Fix minimum in round rateMaxime Ripard2017-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The previous code was always taking 1 as the minimum in it's round_rate function, ignoring entirely what was set as minimum in the clock definition. Make sure that's not the case anymore. Fixes: 2beaa601c849 ("clk: sunxi-ng: Implement minimum for multipliers") Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: Implement factors offsetsMaxime Ripard2017-01-238-29/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The factors we've seen so far all had an offset of one. However, on the earlier Allwinner SoCs, some factors could have no offset at all, meaning that the value computed to reach the rate we want to use was the one we had to program in the registers. Implement an additional field for the factors that can have such an offset (linears, not based on a power of two) to specify that offset. This offset is not linked to the extremums that can be specified in those structures too. The minimum and maximum are representing the range of values we can use to try to compute the best rate. The offset comes later on when we want to set the best value in the registers. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: multiplier: Add fractional supportMaxime Ripard2017-01-232-0/+10
| | | | | | | | | | | | | | | | | | | | Some clocks on the earlier SoCs such as the video PLLs are multipliers with fractional settings. Support those cases. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
| * clk: sunxi-ng: add support for V3s CCUIcenowy Zheng2017-01-206-0/+851
| | | | | | | | | | | | | | | | | | | | V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks about CSI, are different, which makes it to need a new CCU driver. Add such a new driver for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * dt-bindings: add device binding for the CCU of Allwinner V3sIcenowy Zheng2017-01-201-0/+1
| | | | | | | | | | | | | | | | | | Allwinner V3s is now driven by sunxi-ng CCU driver. Add devicetree binding for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-digMylène Josserand2017-01-171-1/+1
| | | | | | | | | | | | | | | | | | The audio DAI needs to set the clock rates of the ac-dig clock. To make it possible, the parent PLL audio clock rates should also be changed. This is possible via "CLK_SET_RATE_PARENT" flag. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: A31: Fix spdif clock registerMarcus Cooper2017-01-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | As the SPDIF was rarely documented on the earlier Allwinner SoCs it was assumed that it had a similar clock register to the one described in the H3 User Manual. However this is not the case and it looks to shares the same setup as the I2S clock registers. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33Icenowy Zheng2017-01-021-1/+1
| | | | | | | | | | | | | | | | | | | | The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to be changeable by changing the rate of PLL_CPUX. Add CLK_SET_RATE_PARENT flag to this clock. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: fix PLL_CPUX adjusting on A33Icenowy Zheng2017-01-021-0/+10
| | | | | | | | | | | | | | | | | | | | | | When adjusting PLL_CPUX on A33, the PLL is temporarily driven too high, and the system hangs. Add a notifier to avoid this situation by temporarily switching to a known stable 24 MHz oscillator. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: fix PLL_CPUX adjusting on H3Ondrej Jirman2017-01-021-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | When adjusting PLL_CPUX on H3, the PLL is temporarily driven too high, and the system becomes unstable (oopses or hangs). Add a notifier to avoid this situation by temporarily switching to a known stable 24 MHz oscillator. Signed-off-by: Ondrej Jirman <megous@megous.com> Tested-by: Lutz Sammer <johns98@gmx.net> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | clk: qcom: SDHCI enablement on Nexus 5X / 6PJeremy McNicoll2017-01-271-0/+18
| | | | | | | | | | | | | | | | Add missing clock branch to enable onboard storage for msm899(2/4). Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | dt-bindings: qcom: clk: Add missing binding for SDCHI enablement on Nexus 5X/6PJeremy McNicoll2017-01-271-0/+1
| | | | | | | | | | | | | | | | AHB clock branch is needed in order to enable SDHCI on msm899(2/4). Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung into ↵Stephen Boyd2017-01-277-32/+70
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next Pull Samsung clk driver updates from Sylwester Nawrocki: - Exporting clock IDs for Exynos5433 SoC MIPI DSI DPHY - Exynos PLL code updates and overall minor clean-ups * tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung: clk: samsung: mark s3c...._clk_sleep_init() as __init clk: samsung: Add enable/disable support for PLL35XX clocks clk: samsung: exynos5433: Correct typos in SoC name clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
| * | clk: samsung: mark s3c...._clk_sleep_init() as __initMartin Kaiser2017-01-274-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions are referencing s3c...._clk_regs[], which are marked as __initdata. When compiling with CONFIG_DEBUG_SECTION_MISMATCH=y, this produces warnings like WARNING: vmlinux.o(.text+0x198350): Section mismatch in reference from the function s3c2410_clk_sleep_init() to the (unknown reference) .init.data:(unknown) Mark the s3c...._clk_sleep_init() functions as __init in order to fix this. Fixes: ca2e90ac1809 ("clk: samsung: add clock controller driver for s3c2412") Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * | clk: samsung: Add enable/disable support for PLL35XX clocksMarek Szyprowski2017-01-271-7/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some PLLs might be disabled by default after turning off and then on a power domain which they belongs to. To avoid configuring a disabled PLL, add proper code for handling PLL enable/disable. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * | clk: samsung: exynos5433: Correct typos in SoC nameMarek Szyprowski2017-01-271-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes simple typos in Exynos5433 clocks driver. The SoC name was referred a few times as '5443' instead of '5433'. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * | clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL ratesMarek Szyprowski2017-01-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Default clock configuration applied by the bootloader for TM2 and TM2e boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure such configuration for those boards with 'assigned-clock-*' properties, parameters for those two additional rates are needed. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * | clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocksMarek Szyprowski2017-01-272-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed to setup initial clock configuration for display subsystem in device tree in order to avoid dependency on the configuration left by the bootloader. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* | | Merge tag 'clk-renesas-for-v4.11-tag2' of ↵Stephen Boyd2017-01-275-18/+150
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: - Use CLK_IS_CRITICAL to handle critical clocks, - Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1, - Add IIC-DVFS clocks for R-Car H3 and M3-W, - Minor cleanups. * tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add IIC-DVFS clock clk: renesas: r8a7795: Add IIC-DVFS clock clk: renesas: cpg-mssr: Add support for reset control clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lock clk: renesas: cpg-mssr: Document suitability for RZ/G1 dt-bindings: clock: renesas: cpg-mssr: Document reset control support clk: renesas: mstp: Reformat cpg_mstp_clock_register() for git diff clk: renesas: mstp: Make INTC-SYS a critical clock clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICAL
| * | | clk: renesas: r8a7796: Add IIC-DVFS clockKhiem Nguyen2017-01-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DVFS clock for R8A7796 SoC. Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: r8a7795: Add IIC-DVFS clockKeita Kobayashi2017-01-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DVFS clock for R8A7795 SoC. Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: cpg-mssr: Add support for reset controlGeert Uytterhoeven2017-01-271-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add optional support for the Reset Control feature of the Renesas Clock Pulse Generator / Module Standby and Software Reset module on R-Car Gen2, R-Car Gen3, and RZ/G1 SoCs. This allows to reset SoC devices using the Reset Controller API. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | | clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lockGeert Uytterhoeven2017-01-271-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The spinlock is used to protect Read-Modify-Write register accesses, which won't be limited to SMSTPCR register accesses. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: renesas: cpg-mssr: Document suitability for RZ/G1Geert Uytterhoeven2017-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Renesas CPG/MSSR driver is already in active use for RZ/G1 since commits c0b2d75d2a4bf6a3 ("clk: renesas: cpg-mssr: Add R8A7743 support") and 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | dt-bindings: clock: renesas: cpg-mssr: Document reset control supportGeert Uytterhoeven2017-01-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document properties needed to use the Reset Control feature of the Renesas Clock Pulse Generator / Module Standby and Software Reset module. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | clk: renesas: mstp: Reformat cpg_mstp_clock_register() for git diffGeert Uytterhoeven2017-01-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the function header of cpg_mstp_clock_register() is split in an unusual way, "git diff" gets confused when changes to the body of the function are made, and attributes them to the wrong function. Reformat the function header to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: renesas: mstp: Make INTC-SYS a critical clockGeert Uytterhoeven2017-01-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | INTC-SYS is the module clock for the GIC. Accessing the GIC while it is disabled causes: Unhandled fault: asynchronous external abort (0x1211) at 0x00000000 Currently, the GIC-400 driver cannot enable its module clock for several reasons: - It does not use a platform device, so Runtime PM is not an option, - gic_of_init() runs before any clocks are registered, so it cannot enable the clock explicitly, - gic_of_init() cannot return -EPROBE_DEFER, as IRQCHIP_DECLARE() doesn't support deferred probing. Hence we have to keep on relying on the boot loader for enabling the module clock. To prevent the module clock from being disabled when the CCF core thinks it is unused, and thus causing a system lock-up, add a check to the MSTP clock driver and enable CLK_IS_CRITICAL. This will make sure the module clock is never disabled. This is a hard dependency for describing the INTC-SYS clock in DT on R-Mobile APE6 and R-Car Gen2. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICALGeert Uytterhoeven2017-01-231-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the Renesas CPG/MSSR driver was introduced, it was anticipated that critical clocks would be handled through a new CLK_ENABLE_HAND_OFF flag soon. However, CLK_ENABLE_HAND_OFF never made it upstream. Instead, commit 32b9b10961860860 ("clk: Allow clocks to be marked as CRITICAL") introduced CLK_IS_CRITICAL, a flag with slightly differing semantics. Still, it can be used to prevent e.g. the GIC module clock from being turned off, until the GIC-400 driver has full support for Runtime PM. Hence migrate the Renesas CPG/MSSR driver from CLK_ENABLE_HAND_OFF to CLK_IS_CRITICAL. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* | | | clk: mvebu: support for 98DX3236 SoCChris Packham2017-01-275-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz. The clock gating options are a subset of those on the Armada XP. The core clock divider is different to the Armada XP also. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | | platform/x86: fix typo in commentPierre-Louis Bossart2017-01-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | s/Acumulate/Accumulate/ Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | | platform/x86: Enable Atom PMC platform clocksIrina Tirdea2017-01-262-3/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BayTrail and CherryTrail platforms provide platform clocks through their Power Management Controller (PMC). The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks are available for general system use, where appropriate. For example, the usage for platform clocks suggested in the datasheet is the following: PLT_CLK[0..2] - Camera PLT_CLK[3] - Audio Codec PLT_CLK[4] - PLT_CLK[5] - COMMs Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | | arch/x86/platform/atom: Move pmc_atom to drivers/platform/x86Irina Tirdea2017-01-267-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pmc_atom driver does not contain any architecture specific code. It only enables the SoC Power Management Controller driver for BayTrail and CherryTrail platforms. Move the pmc_atom driver from arch/x86/platform/atom to drivers/platform/x86. Also clean-up and reorder include files by alphabetical order in pmc_atom.h Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | | clk: x86: Add Atom PMC platform clocksIrina Tirdea2017-01-263-0/+416
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BayTrail and CherryTrail platforms provide platform clocks through their Power Management Controller (PMC). The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks are available for general system use, where appropriate, and each have Control & Frequency register fields associated with them. Port from legacy by Pierre Bossart, integration in clock framework by Irina Tirdea Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | | clk: Make x86/ conditional on CONFIG_COMMON_CLKPierre-Louis Bossart2017-01-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix Makefile for x86 support, dependency on CONFIG_COMMON_CLK was not explicit Fixes: 701190fd7419 ('clk: x86: add support for Lynxpoint LPSS clocks') Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-19 13:01:37 +0000