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* clk: samsung: fix cpu clock's flags checkingBartlomiej Zolnierkiewicz2015-09-221-5/+5
* drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_xGabriel Fernandez2015-09-172-10/+10
* clk: check for invalid parent index of orphans in __clk_init()Mans Rullgard2015-09-161-1/+2
* clk: tegra: dfll: Properly protect OPP listThierry Reding2015-09-161-1/+7
* clk: rockchip: add critical clock for rk3368Heiko Stübner2015-09-141-0/+6
* clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188Romain Perier2015-09-101-0/+1
* clk: rockchip: add pclk_cpu to the list of rk3188 critical clocksMichael Niewoehner2015-09-101-0/+1
* clk: rockchip: handle critical clocks after registering all clocksHeiko Stuebner2015-09-101-2/+5
* clk: Hi6220: separately build stub clock driverLeo Yan2015-09-032-2/+9
* clk: h8s2678: Fix compile errorGuenter Roeck2015-09-021-0/+1
* clk: s5pv210: add missing call to samsung_clk_of_add_provider()Marek Szyprowski2015-08-271-0/+2
* clk: pistachio: correct critical clock listDamien.Horsley2015-08-261-5/+14
* clk: pistachio: Fix PLL rate calculation in integer modeZdenko Pulitika2015-08-261-2/+46
* clk: pistachio: Fix override of clk-pll settings from boot loaderZdenko Pulitika2015-08-261-3/+2
* clk: pistachio: Fix 32bit integer overflowsZdenko Pulitika2015-08-262-21/+19
* clk: tegra: Fix some static checker problemsStephen Boyd2015-08-252-7/+9
* Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd2015-08-2513-9/+2396
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| * clk: tegra: Add the DFLL as a possible parent of the cclk_g clockTuomas Tynkkynen2015-07-161-1/+3
| * clk: tegra: Save/restore CCLKG_BURST_POLICY on suspendTuomas Tynkkynen2015-07-161-0/+14
| * clk: tegra: Add Tegra124 DFLL clocksource platform driverTuomas Tynkkynen2015-07-164-4/+172
| * clk: tegra: Add DFLL DVCO reset control for Tegra124Paul Walmsley2015-07-162-0/+80
| * clk: tegra: Introduce ability for SoC-specific reset control callbacksMikko Perttunen2015-07-162-8/+34
| * clk: tegra: Add functions for parsing CVB tablesTuomas Tynkkynen2015-07-163-0/+208
| * clk: tegra: Add closed loop support for the DFLLTuomas Tynkkynen2015-07-161-3/+663
| * clk: tegra: Add library for the DFLL clock source (open-loop mode)Tuomas Tynkkynen2015-07-163-0/+1150
| * clk: tegra: Add binding for the Tegra124 DFLL clocksourceTuomas Tynkkynen2015-07-161-0/+79
* | clk: qcom: Fix MSM8916 prng clock enable bitGeorgi Djakov2015-08-251-1/+1
* | clk: Add missing header for 'bool' definition to clk-conf.hChen-Yu Tsai2015-08-251-0/+2
* | drivers/clk: appropriate __init annotation for const dataNicolas Pitre2015-08-242-3/+3
* | clk: rockchip: register pll mux before pll itselfHeiko Stuebner2015-08-241-31/+32
* | clk: add bindings for the Ux500 clocksLinus Walleij2015-08-241-0/+64
* | clk/ARM: move Ux500 PRCC bases to the device treeLinus Walleij2015-08-246-176/+225
* | clk: remove duplicated code with __clk_set_parent_afterDong Aisheng2015-08-241-7/+1
* | clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd2015-08-2418-70/+70
* | clk: Constify clk_hw argument to provider APIsStephen Boyd2015-08-242-14/+15
* | clk: Hi6220: add stub clock driverLeo Yan2015-08-243-2/+278
* | dt-bindings: clk: Hi6220: Document stub clock driverLeo Yan2015-08-241-1/+18
* | dt-bindings: arm: Hi6220: add doc for SRAM controllerLeo Yan2015-08-241-0/+18
* | clk: atlas7: fix pll missed divide NR in fraction modeGuo Zeng2015-08-241-0/+1
* | clk: atlas7: fix bit field and its root clk for coresight_tpiuGuo Zeng2015-08-241-1/+1
* | clk: atlas7: replace dto resolution magic number by macroYibo Cai2015-08-241-5/+8
* | clk: atlas7: fix integer overflow in dto rate calculationYibo Cai2015-08-241-2/+2
* | clk: atlas7: export mux clks so that consumers can get themGuo Zeng2015-08-241-2/+3
* | clk: atlas7: add lost pwm unit clksGuo Zeng2015-08-241-0/+4
* | clk: socfpga: Add a second parent option for the dbg_base_clkDinh Nguyen2015-08-242-4/+15
* | clk: ux500: delete the non-DT U8500 clock implementationLinus Walleij2015-08-243-528/+0
* | clk: Remove unused provider APIsStephen Boyd2015-08-242-82/+16
* | clk: si5351: Convert __clk_get_name() to clk_hw_get_name()Stephen Boyd2015-08-241-8/+8
* | drm/msm/dsi: Convert to clk_hw based provider APIsStephen Boyd2015-08-241-2/+2
* | clk: versatile: Switch to assigned clock parentsStephen Boyd2015-08-242-62/+27
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