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* Merge tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgup...Linus Torvalds2015-07-01106-2333/+6998
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| * ARC: Fix build failures for ARCompact in linux-next after ARCv2 supportVineet Gupta2015-06-282-9/+3
| * ARCv2: Allow older gcc to cope with new regime of ARCv2/ARCompact supportVineet Gupta2015-06-281-1/+1
| * ARCv2: [vdk] dts files and defconfig for HS38 VDKRuud Derwig2015-06-2510-0/+490
| * ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x coresVineet Gupta2015-06-2510-12/+720
| * ARC: [axs101] Prepare for AXS103Alexey Brodkin2015-06-252-17/+21
| * ARCv2: [nsim*hs*] Support simulation platforms for HS38x coresVineet Gupta2015-06-259-0/+601
| * ARCv2: All bits in place, allow ARCv2 buildsVineet Gupta2015-06-251-5/+4
| * ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)Vineet Gupta2015-06-253-2/+85
| * ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelockVineet Gupta2015-06-251-2/+12
| * ARC: Reduce bitops lines of code using macrosVineet Gupta2015-06-251-333/+144
| * ARCv2: barriersVineet Gupta2015-06-253-4/+87
| * arch: conditionally define smp_{mb,rmb,wmb}Vineet Gupta2015-06-251-0/+25
| * ARC: add smp barriers around atomics per Documentation/atomic_ops.txtVineet Gupta2015-06-254-0/+89
| * ARC: add compiler barrier to LLSC based cmpxchgVineet Gupta2015-06-251-4/+5
| * ARCv2: SMP: intc: IDU 2nd level intc for dynamic IRQ distributionVineet Gupta2015-06-222-1/+228
| * ARCv2: SMP: clocksource: Enable Global Real Time counterVineet Gupta2015-06-224-0/+56
| * ARCv2: SMP: ARConnect debug/robustnessVineet Gupta2015-06-223-11/+72
| * ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et alVineet Gupta2015-06-227-8/+230
| * ARC: make plat_smp_ops weak to allow over-ridesVineet Gupta2015-06-221-1/+1
| * ARCv2: clocksource: Introduce 64bit local RTC counterVineet Gupta2015-06-223-2/+62
| * ARCv2: extable: Enable sorting at build timeVineet Gupta2015-06-221-0/+5
| * ARCv2: Adhere to Zero Delay loop restrictionVineet Gupta2015-06-223-15/+41
| * ARCv2: optimised string/mem lib routinesClaudiu Zissulescu2015-06-224-2/+411
| * ARCv2: MMUv4: support aliasing icache configVineet Gupta2015-06-222-4/+14
| * ARCv2: MMUv4: cache programming model changesVineet Gupta2015-06-224-18/+104
| * ARCv2: MMUv4: TLB programming Model changesVineet Gupta2015-06-226-5/+114
| * ARCv2: STAR 9000814690: Really Re-enable interrupts to avoid deadlocksVineet Gupta2015-06-221-0/+5
| * ARCv2: STAR 9000808988: signals involving Delay SlotVineet Gupta2015-06-222-7/+12
| * ARCv2: STAR 9000793984: Handle return from intr to Delay SlotVineet Gupta2015-06-223-0/+53
| * ARCv2: Support for ARCv2 ISA and HS38x coresVineet Gupta2015-06-2222-33/+737
| * ARCv2: [intc] HS38 core interrupt controllerVineet Gupta2015-06-224-0/+282
| * ARC: uncached base is hard constant for ARC, don't save itVineet Gupta2015-06-222-3/+2
| * ARC: intc: split into ARCompact ISA specific, common bitsVineet Gupta2015-06-197-379/+412
| * ARC: Make way for pt_regs != user_regs_structVineet Gupta2015-06-192-9/+137
| * ARC: entry.S: [arcompact] simplify SWITCH_TO_KERNEL_STKVineet Gupta2015-06-191-36/+35
| * ARC: entry.S: use single EXCEPTION_PROLOGUEVineet Gupta2015-06-191-8/+6
| * ARC: entry.S: micro-optimize Trap handlerVineet Gupta2015-06-192-4/+5
| * ARC: entry.S: move some code around for cache locality in return pathVineet Gupta2015-06-192-48/+52
| * ARC: entry.S: split into ARCompact ISA specific, common bitsVineet Gupta2015-06-195-681/+711
| * ARC: entry.S: Ensure that restore_regs is local to compilation unitVineet Gupta2015-06-191-4/+4
| * ARC: entry.S: comments cleanupVineet Gupta2015-06-191-26/+20
| * ARC: entry.S: Trap handler to use r10 for syscall vs. brkpt decisionVineet Gupta2015-06-191-2/+2
| * ARC: entry.S: FAKE_RET_FROM_EXCPN can always use r9Vineet Gupta2015-06-192-21/+19
| * ARC: entry.S: confine EXCEPTION_* macros to one fileVineet Gupta2015-06-192-15/+17
| * ARC: entry.S: canonical'ize EXCEPTION_{PROLOGUE,EPILOGUE}Vineet Gupta2015-06-192-18/+3
| * ARC: entry.S: Introduce INTERRUPT_{PROLOGUE,EPILOGUE}Vineet Gupta2015-06-193-79/+23
| * ARC: entry.S: common'ize scrtach reg freeup in intr + exceptionsVineet Gupta2015-06-192-27/+18
| * ARC: untangle cache flush loopVineet Gupta2015-06-191-25/+55
| * ARC: cacheflush: No need to retain DC_CTRL from __before_dc_op()Vineet Gupta2015-06-191-20/+19
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