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| * | drm/i915: Send TP1 TP2/3 even when panel claims no NO_TRAIN_ON_EXIT.Rodrigo Vivi2015-11-181-4/+0
| * | drm/i915: PSR: Don't Skip aux handshake on DP_PSR_NO_TRAIN_ON_EXIT.Rodrigo Vivi2015-11-181-1/+0
| * | drm/i915: Reduce PSR re-activation time for VLV/CHV.Rodrigo Vivi2015-11-181-2/+1
| * | drm/i915: Delay first PSR activation.Rodrigo Vivi2015-11-181-2/+16
| * | drm/i915: Type safe register read/writeVille Syrjälä2015-11-1835-1573/+1540
| * | drm/i915: Add missing ')' to SKL_PS_ECC_STAT defineVille Syrjälä2015-11-181-1/+1
| * | drm/i915: Add 'offset' to uncore funcsVille Syrjälä2015-11-181-23/+25
| * | drm/i915: Pull the vgpu uncore funcs apart from the rest of gen6+Ville Syrjälä2015-11-181-26/+54
| * | drm/i915: Turn vgpu pdps into an arrayVille Syrjälä2015-11-182-15/+8
| * | drm/i915: Wrap context LRI init in a macroVille Syrjälä2015-11-181-51/+40
| * | drm/i915: Give names to more ring registersVille Syrjälä2015-11-182-11/+19
| * | drm/i915: Wrap ASSIGN_CTX_{PDP,PM4L} in do {} while(0)Ville Syrjälä2015-11-181-4/+4
| * | drm/i915: Add wa_ctx_emit_reg()Ville Syrjälä2015-11-181-4/+6
| * | drm/i915: Add functions to emit register offsets to the ringVille Syrjälä2015-11-1810-23/+33
| * | drm/i915: Make the cmd parser 64bit regs explicitVille Syrjälä2015-11-182-14/+35
| * | drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctlVille Syrjälä2015-11-183-12/+22
| * | drm/i915: s/0x50/RING_PSMI_CTL/Ville Syrjälä2015-11-181-1/+1
| * | drm/i915: Parametrize MOCS registersVille Syrjälä2015-11-182-31/+40
| * | drm/i915: Parametrize L3 error registersVille Syrjälä2015-11-183-9/+6
| * | drm/i915: Prefix raw register defines with underscoreVille Syrjälä2015-11-181-131/+131
| * | drm/i915: Streamline gpio_mmio_base deductionVille Syrjälä2015-11-181-8/+7
| * | drm/i915: Store DVO SRCDIM register offset under intel_dvo_deviceVille Syrjälä2015-11-182-14/+10
| * | drm/i915: s/is_sdvob/enum port/Ville Syrjälä2015-11-183-23/+32
| * | drm/i915: s/PCH_DP_/PORT_/ in intel_trans_dp_port_sel() and move it next to i...Ville Syrjälä2015-11-183-23/+19
| * | pci: Decouple quirks.c from i915_reg.hVille Syrjälä2015-11-181-1/+3
| * | drm/i915: Rely on TEST_SINK_START instead of tracking Sink CRC state on dev_p...Rodrigo Vivi2015-11-182-13/+6
| * | drm/i915: Stop tracking last calculated Sink CRC.Rodrigo Vivi2015-11-182-32/+9
| * | drm/i915: Make Sink crc calculation waiting for counter to reset.Rodrigo Vivi2015-11-181-1/+18
| * | drm/i915: Allow 1 vblank to let Sink CRC calculation to start or stop.Rodrigo Vivi2015-11-181-0/+4
| * | drm/i915/skl: Remove unused suspend and resume callbacksPatrik Jakobsson2015-11-171-17/+0
| * | drm/i915/gen9: Add boot parameter for disabling DC6Patrik Jakobsson2015-11-173-3/+18
| * | drm/i915/gen9: Turn DC handling into a power wellPatrik Jakobsson2015-11-174-35/+90
| * | drm/i915: Explain usage of power well IDs vs bit groupsPatrik Jakobsson2015-11-171-0/+4
| * | drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()Patrik Jakobsson2015-11-171-3/+0
| * | drm/i915: Add a modeset power domainPatrik Jakobsson2015-11-172-0/+3
| * | drm/i915: Remove distinction between DDI 2 vs 4 lanesPatrik Jakobsson2015-11-174-78/+45
| * | drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINSVille Syrjälä2015-11-171-5/+1
| * | drm/i915: Introduce a gmbus power domainVille Syrjälä2015-11-176-40/+13
| * | drm/i915: Clean up AUX power domain handlingVille Syrjälä2015-11-173-34/+59
| * | drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6Patrik Jakobsson2015-11-171-18/+17
| * | drm/i915: Don't trust CSR program memory contentsPatrik Jakobsson2015-11-171-7/+3
| * | drm/i915: fix handling of the disable_power_well module optionImre Deak2015-11-172-2/+16
| * | drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 enablingImre Deak2015-11-171-5/+0
| * | drm/i915/skl: make sure LCPLL is disabled when uniniting CDCLKImre Deak2015-11-171-10/+4
| * | drm/i915/skl: disable DC states before display core init/uninitImre Deak2015-11-171-0/+4
| * | drm/i915/gen9: simplify DC toggling codeImre Deak2015-11-172-36/+28
| * | drm/i915/skl: don't toggle PW1 and MISC power wells on-demandImre Deak2015-11-171-27/+9
| * | drm/i915/skl: init/uninit display core as part of the HW power domain stateImre Deak2015-11-175-21/+61
| * | drm/i915: rename intel_power_domains_resume to *_sync_hwImre Deak2015-11-171-2/+2
| * | drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequencesDamien Lespiau2015-11-174-4/+35
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