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| | | | | * | | | clk: qoriq: increase array size of cmux_to_groupYogesh Gaur2019-04-251-2/+2
| | | | | * | | | dt-bindings: qoriq-clock: Add ls1028a chip compatible stringYuantian Tang2019-04-251-0/+1
| | | | | * | | | clk: qoriq: Add ls1028a clock configurationYuantian Tang2019-04-251-0/+68
| | | | | * | | | clk: qoriq: add more PLL divider clocks supportYuantian Tang2019-04-251-2/+3
| | | | | * | | | dt-bindings: qoriq-clock: add more PLL divider clocks supportYuantian Tang2019-04-251-2/+2
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| | | | * | | | Merge tag 'v5.2-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/...Stephen Boyd2019-04-254-26/+60
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| | | | | * | | clk: rockchip: undo several noc and special clocks as critical on rk3288Douglas Anderson2019-04-231-9/+4
| | | | | * | | clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-typeFinley Xiao2019-04-122-3/+29
| | | | | * | | clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288Douglas Anderson2019-04-121-0/+11
| | | | | * | | clk: rockchip: Limit use of USB PHY clock to USB on rk3288Matthias Kaehlcke2019-04-121-2/+2
| | | | | * | | clk: rockchip: Fix video codec clocks on rk3288Douglas Anderson2019-04-121-2/+2
| | | | | * | | clk: rockchip: Make rkpwm a critical clock on rk3288Douglas Anderson2019-04-111-1/+3
| | | | | * | | clk: rockchip: fix wrong clock definitions for rk3328Jonas Karlman2019-03-181-9/+9
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| | | * | | | Merge tag 'sunxi-clk-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/...Stephen Boyd2019-04-1910-36/+95
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| | | | * | | clk: sunxi-ng: sun5i: Export the MBUS clockMaxime Ripard2019-04-102-5/+1
| | | | * | | clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclkChen-Yu Tsai2019-04-091-2/+3
| | | | * | | clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rateJernej Skrabec2019-04-041-3/+3
| | | | * | | clk: sunxi-ng: h6: Preset hdmi-cec clock parentJernej Skrabec2019-04-031-0/+11
| | | | * | | clk: sunxi: Add Kconfig optionsMaxime Ripard2019-03-213-22/+71
| | | | * | | clk: sunxi-ng: f1c100s: fix USB PHY gate bit offsetIcenowy Zheng2019-03-181-1/+1
| | | | * | | clk: sunxi-ng: Allow DE clock to set parent rateJernej Skrabec2019-03-183-3/+5
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| | * | | | clk: lochnagar: Add support for the Cirrus Logic LochnagarCharles Keepax2019-04-233-0/+344
| | * | | | clk: lochnagar: Add initial binding documentationCharles Keepax2019-04-231-0/+93
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| * / / / clk: hi3660: Mark clk_gate_ufs_subsys as criticalLeo Yan2019-04-191-1/+5
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*-------. \ \ \ Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-...Stephen Boyd2019-05-0714-91/+181
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| | | | | * | | | clk: zynqmp: use structs for clk query responsesMichael Tretter2019-04-192-77/+99
| | | | | * | | | clk: zynqmp: fix check for fractional clockMichael Tretter2019-04-111-3/+6
| | | | | * | | | clk: zynqmp: do not export zynqmp_clk_register_* functionsMichael Tretter2019-04-112-2/+0
| | | | | * | | | clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parentsMichael Tretter2019-04-111-1/+1
| | | | | * | | | drivers: clk: Update clock driver to handle clock attributeRajan Vaja2019-04-111-13/+29
| | | | | * | | | drivers: clk: zynqmp: Allow zero divisor valueRajan Vaja2019-04-111-0/+7
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| | | | * | | | clk: ingenic: jz4725b: Add UDC PHY clockPaul Cercueil2019-04-111-0/+6
| | | | * | | | dt-bindings: clock: jz4725b-cgu: Add UDC PHY clockPaul Cercueil2019-04-111-0/+1
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| | | * | | | Merge tag 'clk-v5.2-samsung' of https://git.kernel.org/pub/scm/linux/kernel/g...Stephen Boyd2019-04-192-1/+3
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| | | | * | | clk: samsung: exynos5410: Add gate clock for ADCKrzysztof Kozlowski2019-03-221-0/+1
| | | | * | | clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410Krzysztof Kozlowski2019-03-221-0/+1
| | | | * | | clk: samsung: dt-bindings: Put CLK_UART3 in orderKrzysztof Kozlowski2019-03-221-1/+1
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| | * / / / clk: Aspeed: Setup video engine clockingEddie James2019-04-181-3/+39
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| * | | | clk: mvebu: fix spelling mistake "gatable" -> "gateable"Colin Ian King2019-04-182-3/+3
| * | | | clk: ux500: add range to usleep_rangeNicholas Mc Guire2019-04-111-1/+2
| * | | | clk: tegra: Make tegra_clk_super_mux_ops staticYueHaibing2019-04-111-1/+1
| * | | | clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5Ding Xiang2019-04-111-3/+1
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*-----. \ \ \ Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be'...Stephen Boyd2019-05-0736-710/+2424
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| | | | * | | | clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski2019-04-2319-83/+68
| | | | * | | | clk: core: remove powerpc special handlingJonas Gorski2019-04-231-16/+0
| | | | * | | | powerpc/512x: mark clocks as big endianJonas Gorski2019-04-231-3/+6
| | | | * | | | clk: mux: add explicit big endian supportJonas Gorski2019-04-232-3/+23
| | | | * | | | clk: multiplier: add explicit big endian supportJonas Gorski2019-04-232-3/+23
| | | | * | | | clk: gate: add explicit big endian supportJonas Gorski2019-04-232-3/+23
| | | | * | | | clk: fractional-divider: add explicit big endian supportJonas Gorski2019-04-232-3/+23
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 14:41:28 +0000