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* irqchip: mips-gic: Remove gic_map_to_pin()Paul Burton2017-09-042-17/+1
| | | | | | | | | | | | | | Remove the gic_map_to_pin() function in favour of using the new write_gic_map_pin() accessor function which isn't any more complex to use & allows us to drop a level of abstraction. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17032/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Remove gic_set_dual_edge()Paul Burton2017-09-042-40/+5
| | | | | | | | | | | | | | | | Remove the gic_set_dual_edge() function in favour of using the new change_gic_dual() accessor function which provides equivalent functionality. This also allows us to remove the gic_update_bits() function which gic_set_dual_edge() was the last user of, along with the GIC_INTR_OFS() & GIC_INTR_BIT() macros. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Remove gic_set_trigger()Paul Burton2017-09-042-18/+6
| | | | | | | | | | | | | | Remove the gic_set_trigger() function in favour of using the new change_gic_trig() accessor function which provides equivalent functionality. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17030/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Remove gic_set_polarity()Paul Burton2017-09-042-17/+5
| | | | | | | | | | | | | | Remove the gic_set_polarity() function in favour of using the new change_gic_pol() accessor function which provides equivalent functionality. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17029/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Drop gic_(re)set_mask() functionsPaul Burton2017-09-042-19/+3
| | | | | | | | | | | | | | The gic_set_mask() & gic_reset_mask() functions are now no more convenient to call than the write_gic_smask() or write_gic_rmask() accessor functions. Remove the layer of abstraction. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17028/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Simplify gic_local_irq_domain_map()Paul Burton2017-09-042-47/+16
| | | | | | | | | | | | | | | | | | | | Simplify gic_local_irq_domain_map() by: - Moving the check for invalid IRQs outside of the loop. - Moving the decision about whether to use gic_cpu_pin or timer_cpu_pin outside of the loop. - Using the new write_gic_vo_map() accessor function to avoid the need to handle each map register separately. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17027/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Simplify shared interrupt pending/mask readsPaul Burton2017-09-042-24/+11
| | | | | | | | | | | | | | Simplify the reads of the bitmaps indicating pending & masked interrupts in gic_handle_shared_int() using the __ioread32_copy() & __ioread64_copy() helper functions. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17026/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add __ioread64_copyPaul Burton2017-09-043-1/+45
| | | | | | | | | | | | | | | | | We currently have __ioread32_copy, __iowrite32_copy & __iowrite64_copy helpers in lib/iomap_copy.c. This patch adds __ioread64_copy to round out the set, allowing copies from I/O memory using 32 or 64 bit reads. [ralf@linux-mips.org: Changed to move all the code of this patch to be applied to arch/mips temporarily.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17025/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Remove gic_read_local_vp_id()Paul Burton2017-09-042-25/+0
| | | | | | | | | | | | | Nothing needs gic_read_local_vp_id() any longer, so remove the dead code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17024/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CPS: Read GIC_VL_IDENT directly, not via irqchip driverPaul Burton2017-09-041-1/+1
| | | | | | | | | | | | | | | | Rather than calling the gic_read_local_vp_id() function from the GIC irqchip driver, call read_gic_vl_ident() to read the GIC_VL_IDENT register directly. This will allow us to remove gic_read_local_vp_id() from the irqchip driver in a further patch, since that driver doesn't actually care about the register's value. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17023/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Remove counter access functionsPaul Burton2017-09-042-117/+0
| | | | | | | | | | | | | The MIPS GIC clocksource driver is no longer using the accessor functions provided by the irqchip driver, so remove them. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17022/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: Use new GIC accessor functionsPaul Burton2017-09-011-3/+3
| | | | | | | | | Use the accessor functions provided by asm/mips-gic.h rather than calling functions provided by the GIC irqchip driver, in preparation for those non-IRQ-related functions being removed from the irqchip driver. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* clocksource: mips-gic-timer: Use new GIC accessor functionsPaul Burton2017-08-301-6/+31
| | | | | | | | | | | | | | | | | Switch from calling functions exported by the GIC interrupt controller to using new accessors provided by asm/mips-gic.h. This will allow the counter-handling functionality to be removed from the interrupt controller driver, where it doesn't really belong, and also allow for inlining of the accesses to the GIC. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17021/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: GIC: Introduce asm/mips-gic.h with accessor functionsPaul Burton2017-08-303-7/+300
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a new header providing accessor functions for the MIPS Global Interrupt Controller (GIC) mirroring those provided for the other 2 components of the MIPS Coherent Processing System (CPS) - the Coherence Manager (CM) & Cluster Power Controller (CPC). This header makes use of the new standardised CPS accessor macros where possible, but does require some custom accessors for cases where we have either a bit or a register per interrupt. A major advantage of this over the existing include/linux/irqchip/mips-gic.h definitions is that code performing accesses can become much simpler, for example this: gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), (unsigned long)trig << GIC_INTR_BIT(intr)); ...can become simply: change_gic_trig(intr, trig); The accessors handle 32 vs 64 bit in the same way as for CM & CPC code, which means that GIC code will also not need to worry about the access size in most cases. They are also accessible outside of drivers/irqchip/irq-mips-gic.c which will allow for simplification in the use of the non-interrupt portions of the GIC (eg. counters) which currently require the interrupt controller driver to expose helper functions for access. This patch doesn't change any existing code over to use the new accessors yet, since a wholesale change would be invasive & difficult to review. Instead follow-on patches will convert code piecemeal to use this new header. The one change to existing code is to rename gic_base to mips_gic_base & make it global, in order to fit in with the naming expected by the standardised CPS accessor macros. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17020/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: SYNC after enabling GIC regionJames Hogan2017-08-301-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | A SYNC is required between enabling the GIC region and actually trying to use it, even if the first access is a read, otherwise its possible depending on the timing (and in my case depending on the precise alignment of certain kernel code) to hit CM bus errors on that first access. Add the SYNC straight after setting the GIC base. [paul.burton@imgtec.com: Changes later in this series increase our likelihood of hitting this by reducing the amount of code that runs between enabling the GIC & accessing it.] Fixes: a7057270c280 ("irqchip: mips-gic: Add device-tree support") Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17019/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Don't use dma_cache_sync to implement fd_cacheflushChristoph Hellwig2017-08-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | The floppy drivers doesn't otherwise use the DMA API, so indirecting through it just for cache flushing in MIPS-specific code just call dma_cache_wback_inv directly. Signed-off-by: Christoph Hellwig <hch@lst.de> Cc: iommu@lists.linux-foundation.org Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Michal Simek <monstr@monstr.eu> Cc: David Howells <dhowells@redhat.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Chris Zankel <chris@zankel.net> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: x86@kernel.org Cc: linux-mips@linux-mips.org Cc: linux-ia64@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-xtensa@linux-xtensa.org Cc: linux-sh@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17183/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: generic: Bump default NR_CPUS to 16Paul Burton2017-08-301-1/+1
| | | | | | | | | | In generic_defconfig set CONFIG_NR_CPUS to 16 rather than 2, which is a rather too low limit for many modern day MIPS systems. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16949/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: generic: Don't explicitly disable CONFIG_USB_SUPPORTPaul Burton2017-08-301-1/+0
| | | | | | | | | | | Leave CONFIG_USB_SUPPORT at its default, allowing board config fragments to make use of USB drivers without needing to override it & trigger warnings from merge_config.sh. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16948/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Make CONFIG_MIPS_MT_SMP default yPaul Burton2017-08-306-4/+2
| | | | | | | | | | | | | | | | | | | | | | On systems that support MT ASE multithreading (ie. VPEs) we are very likely to want to include that support as default. Rather than setting it in various defconfigs, simply make CONFIG_MIPS_MT_SMP default y such that systems which select CONFIG_SYS_SUPPORTS_MULTITHREADING get it by default. As well as allowing us to remove the selection of CONFIG_MIPS_MT_SMP from various defconfigs, this also allows the generated generic defconfigs which derive from generic_defconfig to automatically gain support for MT ASE SMP when building for a suitable (pre-MIPSr6) ISA. For malta_kvm_guest_defconfig CONFIG_MIPS_MT_SMP is explicitly disabled since enabling SMP implicitly disables CONFIG_KVM_GUEST, which depends on CONFIG_BROKEN_ON_SMP. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16947/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Prevent direct use of generic_defconfigPaul Burton2017-08-301-0/+13
| | | | | | | | | | | | | | | Using generic_defconfig directly is unlikely to be what a user actually wants to do - it doesn't specify any particular ISA revision & it doesn't enable any board or driver support, resulting in a largely useless kernel. Prevent users from using it directly, printing a helpful message to point them in the right direction if they attempt to. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16946/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: NI 169445: Only include in 32r2el kernelsPaul Burton2017-08-301-0/+3
| | | | | | | | | | | | | | | | | | | The NI 169445 board uses a little endian MIPS32r2 CPU, and therefore including board support in kernels that are unable to run on such a CPU is pointless. Specify requirements in the board config fragment that cause the NI 169445 board support to only be included in generic kernels that target little endian MIPS32r2 CPUs. For example, NI 169445 support will be included when configuring using 32r2el_defconfig but not when using 64r6_defconfig. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Nathan Sullivan <nathan.sullivan@ni.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16945/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SEAD-3: Only include in 32 bit kernels by defaultPaul Burton2017-08-301-0/+2
| | | | | | | | | | | | | | | The MIPS SEAD-3 development board has only ever been used with 32 bit CPUs, so including support for it in 64 bit kernels is wasteful since those kernels will never run on a SEAD-3. Specify a requirement in the SEAD-3 board config fragment that ensures the board support is only included in 32 bit kernels, by checking that CONFIG_32BIT=y. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16944/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: generic: Allow filtering enabled boards by requirementsPaul Burton2017-08-303-2/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up until now when configuring a generic kernel all board config fragments have been merged by default unless boards are explicitly selected by the user specifying BOARDS=. In many cases this is sub-optimal, since some boards don't make sense to include in some kernels. For example the MIPS SEAD-3 development board has only ever been used with 32 bit CPUs, so including support for the SEAD-3 in a 64 bit kernel is wasteful. This patch introduces support for specifying requirements in board config fragments, using comments formatted like so: # require CONFIG_BLA=y For example the SEAD-3 board could specify that it should only be merged for 32 bit kernels using a requirement line like the following: # require CONFIG_32BIT=y A new generic-board-config.sh script is introduced to handle selecting the board config fragments to merge & calling merge_config.sh to merge them. In order to allow requirements to check Kconfig symbols that are implicitly selected, rather than explicitly specified by generic_defconfig or one of the ISA config fragments, an intermediate .config file is saved & used as a reference when checking requirements. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16943/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CPS: Detect CPUs in secondary clustersPaul Burton2017-08-301-29/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | As a first step towards supporting multi-cluster systems, detect cores & VPs in secondary clusters & record their cluster information in the cpu_data array. The "VP topology" line printed during boot is extended to display multiple clusters. On a single cluster it shows output like the following: VP topology: {4,4} This would indicate a system with 2 cores which each contain 4 VPs. We extend this to cover multiple clusters in a natural way: VP topology: {4,4},{2,2} This would indicate a system with 2 clusters. The first cluster contains 2 cores which each contain 4 VPs. The second cluster contains 2 cores which each contain 2 VPs. Actually booting these cores & VPs is left to further patches once other pieces are in place. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17017/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CPS: Cluster support for topology functionsPaul Burton2017-08-307-48/+136
| | | | | | | | | | | | | | | | | Modify the functions we use to read information about the topology of the system (the number of cores, VPs & IOCUs that it contains) in order to take into account multiple clusters, and provide a new function to determine the number of clusters in the system. Users of these functions are modified only such that they continue to build successfully - having them actually handle multiple clusters is left to further patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17016/ Patchwork: https://patchwork.linux-mips.org/patch/17218/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CPS: Have asm/mips-cps.h include CM & CPC headersPaul Burton2017-08-3020-30/+28
| | | | | | | | | | | | | | | | | | | | | | | | With Coherence Manager (CM) 3.5 information about the topology of the system, which has previously only been available through & accessed from the CM, is now also provided by the Cluster Power Controller (CPC). This includes a new CPC_CONFIG register mirroring GCR_CONFIG, and similarly a new CPC_Cx_CONFIG register mirroring GCR_Cx_CONFIG. In preparation for adjusting functions such as mips_cm_numcores(), which have previously only needed to access the CM, to also access the CPC this patch modifies the way we use the various CPS headers. Rather than having users include asm/mips-cm.h or asm/mips-cpc.h individually we instead have users include asm/mips-cps.h which in turn includes asm/mips-cm.h & asm/mips-cpc.h. This means that users will gain access to both CM & CPC registers by including one header, and most importantly it makes asm/mips-cps.h an ideal location for helper functions which need to access the various components of the CPS. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17015/ Patchwork: https://patchwork.linux-mips.org/patch/17217/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SMP: Allow boot_secondary SMP op to return errorsPaul Burton2017-08-3014-15/+37
| | | | | | | | | | | | | | Allow the boot_secondary SMP op to return an error to __cpu_up(), which will in turn return it to its caller. This will allow SMP implementations to return errors quickly in cases they they know have failed, rather than relying upon __cpu_up() eventually timing out waiting for the cpu_running completion. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17014/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CM: Add cluster & block args to mips_cm_lock_other()Paul Burton2017-08-304-18/+58
| | | | | | | | | | | | | | | | | | | With CM >= 3.5 we have the notion of multiple clusters & can access their CM, CPC & GIC registers via the apporpriate redirect/other register blocks. In order to allow for this introduce cluster & block arguments to mips_cm_lock_other() which configures the redirect/other region to point at the appropriate cluster, core, VP & register block. Since we now have 4 arguments to mips_cm_lock_other() & a common use is likely to be to target the cluster, core & VP corresponding to a particular Linux CPU number we also add a new mips_cm_lock_other_cpu() helper function which handles that without the caller needing to manually pull out the cluster, core & VP numbers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17013/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add CPU cluster number accessorsPaul Burton2017-08-302-0/+21
| | | | | | | | | | | | Introduce cpu_cluster() & cpu_set_cluster() accessor functions in the same vein as cpu_core(), cpu_vpe_id() & their set variants. These will be used in further patches to allow users to get or set a CPUs cluster number. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17012/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Unify checks for sibling CPUsPaul Burton2017-08-305-13/+28
| | | | | | | | | | | | | | | | | | | | Up until now we have open-coded checks for whether CPUs are siblings, with slight variations on whether we consider the package ID or not. This will only get more complex when we introduce cluster support, so in preparation for that this patch introduces a cpus_are_siblings() function which can be used to check whether or not 2 CPUs are siblings in a consistent manner. By checking globalnumber with the VP ID masked out this also has the neat side effect of being ready for multi-cluster systems already. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Rafael J. Wysocki <rjw@rjwysocki.net> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17011/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Store core & VP IDs in GlobalNumber-style variablePaul Burton2017-08-302-26/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch modifies the way we store core & VP IDs such that we store them in a single 32 bit integer whose format matches that of the MIPSr6 GlobalNumber register. Whereas we have previously stored core & VP IDs in separate fields, storing them in a single GlobalNumber-like field: 1) Reduces the size of struct cpuinfo_mips by 4 bytes, and will allow it to not grow when cluster support is added. 2) Gives us a natural place to store cluster number, which matches up with what the architecture provides. 3) Will be useful in the future as a parameter to the MIPSr6 GINVI instruction to specify a target CPU whose icache that instruction should operate on. The cpu_set*() accessor functions are moved out of the asm/cpu-info.h header in order to allow them to use the WARN_ON macro, which is unusable in asm/cpu-info.h due to include ordering. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17010/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Abstract CPU core & VP(E) ID access through accessor functionsPaul Burton2017-08-3016-46/+71
| | | | | | | | | | | | | | | | | | | | | | | | | We currently have fields in struct cpuinfo_mips for the core & VP(E) ID of a particular CPU, and various pieces of code directly access those fields. This patch abstracts such access by introducing accessor functions cpu_core(), cpu_set_core(), cpu_vpe_id() & cpu_set_vpe_id() and having code that needs to access these values call those functions rather than directly accessing the struct cpuinfo_mips fields. This prepares us for changes to the way in which those values are stored in later patches. The cpu_vpe_id() function is introduced even though we already had a cpu_vpe_id() macro for a couple of reasons: 1) It's more consistent with the core, and future cluster, accessors. 2) It ensures a sensible return type without explicit casts. 3) It's generally preferable to use functions rather than macros. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CPS: Use GlobalNumber macros rather than magic numbersPaul Burton2017-08-301-2/+2
| | | | | | | | | | We now have definitions for the GlobalNumber register in asm/mipsregs.h, so use them in place of magic numbers in cps-vec.S. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17008/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add accessor & bit definitions for GlobalNumberPaul Burton2017-08-301-0/+13
| | | | | | | | | | | | | | | | | MIPSr6 introduces a GlobalNumber register, which is required when VPs are implemented (ie. when multi-threading is supported) but otherwise optional. The register contains sufficient information to uniquely identify a VP within a system using its cluster number, core number & VP ID. In preparation for using this register & its fields, introduce an accessor macro for it & define its various bits with the typical style preprocessor macros. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17007/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CPS: Add CM/CPC 3.5 register definitionsPaul Burton2017-08-302-7/+69
| | | | | | | | | | | | Introduce definitions & accessors for a selection of Coherence Manager (CM) & Cluster Power Controller (CPC) registers that are new with CM v3.5 & the MIPS I6500. These are primarily registers that will be used in supporting multiple CPU clusters. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17006/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CPS: Use change_*, set_* & clear_* where appropriatePaul Burton2017-08-303-21/+8
| | | | | | | | | | | Make use of the new change_*, set_* & clear_* accessor functions for CPS (CM, CPC & GIC) registers where doing so makes the code easier to read or shortens it without adversely affecting readability. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17005/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CPS: Introduce register modify (set/clear/change) accessorsPaul Burton2017-08-301-1/+22
| | | | | | | | | | | | For read-write registers introduce accessor functions that simplify the task of modifying a subset of bits within the register. set_* functions set bits to 1, clear_* functions clear bits to 0 & change_* functions set bits specified in a mask to an arbitrary value. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17004/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CPC: Use BIT/GENMASK for register fields, order & drop shiftsPaul Burton2017-08-304-42/+49
| | | | | | | | | | | | | | | | | | | | | | Tidy up asm/mips-cpc.h in a similar way to what "MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts" did for asm/mips-cm.h. We use BIT() & GENMASK() to simplify the definition of register fields, drop the _SHF definitions since that information can be found in the _MSK ones, and then drop the _MSK suffix. Fields definitions are moved to be next to the appropriate register definition, making it easier to link the two & keep everything ordered by register address. Comments are added including the name of each register & a brief description of its purpose which helps to understand what registers are for, link them back to hardware documentation or grep for them. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17003/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CPC: Use common CPS accessor generation macrosPaul Burton2017-08-301-41/+22
| | | | | | | | | | | Switch the MIPS Cluster Power Controller (CPC) accessor functions to be generated by the new common Coherent Processing System (CPS) macros shared with the Coherence Manager (CM). Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17002/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CM: Use BIT/GENMASK for register fields, order & drop shiftsPaul Burton2017-08-299-241/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no reason for us not to use BIT() & GENMASK() in asm/mips-cm.h when declaring macros corresponding to register fields. This patch modifies our definitions to do so. The *_SHF definitions are removed entirely - they duplicate information found in the masks, are infrequently used & can be replaced with use of __ffs() where needed. The *_MSK definitions then lose their _MSK suffix which is now somewhat redundant, and users are modified to match. The field definitions are moved to follow the appropriate register's accessor functions, which helps to keep the field definitions in order & to find the appropriate fields for a given register. Whilst here a comment is added describing each register & including its name, which is helpful both for linking the register back to hardware documentation & for grepping purposes. This also cleans up a couple of issues that became obvious as a result of making the changes described above: - We previously had definitions for GCR_Cx_RESET_EXT_BASE & a phony copy of that named GCR_RESET_EXT_BASE - a register which does not exist. The bad definitions were added by commit 497e803ebf98 ("MIPS: smp-cps: Ensure secondary cores start with EVA disabled") and made use of from boot_core(), which is now modified to use the GCR_Cx_RESET_EXT_BASE definitions. - We had a typo in CM_GCR_ERROR_CAUSE_ERRINGO_MSK - we now correctly define this as inFo rather than inGo. Now that we don't duplicate field information between _SHF & _MSK definitions, and keep the fields next to the register accessors, it will be much easier to spot & prevent any similar oddities being introduced in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Thomas Gleixner <tglx@linutronix.de Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17001/ Patchwork: https://patchwork.linux-mips.org/patch/17216/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CM: Specify register size when generating accessorsPaul Burton2017-08-293-115/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | Some CM registers are always 32 bits, or at least only use bits in the lower 32 bits of the register. For these registers it is wasteful for us to generate accessors which bother to check mips_cm_is64 & perform 64 bit accesses. This patch modifies the accessor generation to take into account the size of the register, and for 32 bit registers we generate accessors which only ever perform 32 bit accesses. For 64 bit registers we either perform a 64 bit access or two 32 bit accesses, depending upon the value of mips_cm_is64. Doing this saves us ~1.5KiB of code in a generic 64r6el kernel, and perhaps more importantly simplifies various code paths. This removes the read64_gcr_* accessors, so mips_cm_error_report() is modified to stop using them & instead use the regular read_gcr_* accessors which will return 64 bit values from the 64 bit registers. The new accessor macros are placed in asm/mips-cps.h such that they can be shared by CPC & GIC code in later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17000/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CM: Rename mips_cm_base to mips_gcr_basePaul Burton2017-08-292-8/+8
| | | | | | | | | | | | | | | | | | | | We currently have a mips_cm_base variable which holds the base address of the Coherence Manager (CM) Global Configuration Registers (GCRs), and accessor functions which use the GCR in their names. This works fine, but gets in the way of sharing the code to generate the accessor functions with other blocks (ie. CPC & GIC) because that code would then need to separately handle the name of the base address variable & the name used in the accessor functions. In order to prepare for sharing the accessor generation code between CM, CPC & GIC code this patch renames mips_cm_base to mips_gcr_base such that the "gcr" portion is common to both the base address variable & the accessor function names. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16999/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Add FP emu debugfs stats for individual instructionsAleksandar Markovic2017-08-293-4/+650
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add FP emulation debugfs statistics for individual instructions. The debugfs files that contain counter values are placed in a separate directory called "instructions". This means that the default path for these new stat is "/sys/kernel/debug/mips/fpuemustats/instructions". Each instruction counter is mapped to the debugfs file that has the same name as instruction name. The lowercase is choosen as more commonly used case for instruction names. One example of usage: mips_host::/sys/kernel/debug/mips/fpuemustats/instructions # grep "" * The shortened output of this command is: abs.d:34 abs.s:5711 add.d:10401 add.s:399307 bc1eqz:3199 ... ... ... sub.s:167211 trunc.l.d:375 trunc.l.s:8054 trunc.w.d:421 trunc.w.s:27032 The limitation of this patch is that it handles R6 FP emulation instructions only. There are altogether 114 handled instructions. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Cc: Douglas Leung <douglas.leung@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Petar Jovanovic <petar.jovanovic@imgtec.com> Cc: Raghu Gandham <raghu.gandham@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17145/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Add FP emu debugfs clear functionalityAleksandar Markovic2017-08-291-1/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | Add capability for the user to clear all FP emu debugfs counters. This is achieved by having a special debugfs file "fpuemustats_clear" (under default location "/sys/kernel/debug/mips"). Each access to the file results in setting all counters to zero (it is enough, let's say, to issue a "cat /sys/kernel/debug/mips/fpuemustats_clear"). This functionality already exists for R2 emulation statistics, but was missing for FP emulation statistics. The implementation in this patch is consistent with its R2 emulation counterpart. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Cc: Douglas Leung <douglas.leung@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Petar Jovanovic <petar.jovanovic@imgtec.com> Cc: Raghu Gandham <raghu.gandham@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17144/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Add FP emu debugfs statistics for branchesAleksandar Markovic2017-08-293-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Add FP emu debugfs counter for branches. The new counter is displayed the same way as existing counter, and its default path is /sys/kernel/debug/mips/fpuemustats/. The limitation of this counter is that it counts only R6 branch instructions BC1NEZ and BC1EQZ. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Cc: Douglas Leung <douglas.leung@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Petar Jovanovic <petar.jovanovic@imgtec.com> Cc: Raghu Gandham <raghu.gandham@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17143/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: CLASS.D: Zero bits 32-63 of the resultAleksandar Markovic2017-08-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix content of CLASS.D output bits 32-63 to match hardware behavior. Prior to this patch, bits 32-63 of CLASS.D output were not initialized, causing different 32-63 bits content of CLASS.D, based on circumstances. However, the hardware consistently returns all these bits zeroed. The documentation is not clear whether these bits should be zero or unpredictable. Since technically "all zero" case still can be viewed as belonging to "unpredictable" class of results, it is better to zero bits 32-63. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Cc: Douglas Leung <douglas.leung@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Petar Jovanovic <petar.jovanovic@imgtec.com> Cc: Raghu Gandham <raghu.gandham@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17142/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: RINT.<D|S>: Fix several problems by reimplementationAleksandar Markovic2017-08-296-6/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reimplement RINT.<D|S> kernel emulation so that all RINT.<D|S> specifications are met. For the sake of simplicity, let's analyze RINT.S only. Prior to this patch, RINT.S emulation was essentially implemented as (in pseudocode) <output> = ieee754sp_flong(ieee754sp_tlong(<input>)), where ieee754sp_tlong() and ieee754sp_flong() are functions providing conversion from double to integer, and from integer to double, respectively. On surface, this implementation looks correct, but actually fails in many cases. Following problems were detected: 1. NaN and infinity cases will not be handled properly. The function ieee754sp_flong() never returns NaN nor infinity. 2. For RINT.S, for all inputs larger than LONG_MAX, and smaller than FLT_MAX, the result will be wrong, and the overflow exception will be erroneously set. A similar problem for negative inputs exists as well. 3. For some rounding modes, for some negative inputs close to zero, the return value will be zero, and should be -zero. This is because ieee754sp_flong() never returns -zero. This patch removes the problems above by implementing dedicated functions for RINT.<D|S> emulation. The core of the new function functionality is adapted version of the core of the function ieee754sp_tlong(). However, there are many details that are implemented to match RINT.<D|S> specification. It should be said that the functionality of ieee754sp_tlong() actually closely corresponds to CVT.L.S instruction, and it is used while emulating CVT.L.S. However, RINT.S and CVT.L.S instructions differ in many aspects. This patch fulfills missing support for RINT.<D|S>. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Cc: David S. Miller <davem@davemloft.net> Cc: Douglas Leung <douglas.leung@imgtec.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Hans Verkuil <hans.verkuil@cisco.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Petar Jovanovic <petar.jovanovic@imgtec.com> Cc: Raghu Gandham <raghu.gandham@imgtec.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17141/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: CMP.Sxxx.<D|S>: Prevent occurrences of SIGILL crashesAleksandar Markovic2017-08-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix CMP.Sxxx.<D|S> SIGILL crashes by fixing main switch/case statement in fpu_emul() function so that inadvertent fall-troughs are prevented. Consider, let's say, CMP.SAF.S instruction when one of inputs is zero and another input is a signaling NaN. The desired output is zero, and the exception flag "invalid operation" set. For such case, the main portion of the implementation is within "d_fmt" case of the main "switch/case" statement in fpu_emul() function. The execution will follow one of "if-else" branches that doesn't contain "goto cop1scr;" statement, and will therefore reach the end of "d_fmt" case. It will subsequently fall through to the next case, "l_fmt". After following similar pattern, the execution will fall through to the succeeding case, which is "default". The "default" case contains "return SIGILL;" statement only. This means that the caller application will crash with "illegal instruction" message. It is obvious that above described fall-throughs are unnecessary and harmful. This patch rectifies that behavior by providing "break;" statements at the end of cases "d_fmt" and "l_fmt". There are 22 instructions affected by this problem: CMP.<SAF|SEQ|SLE|SLT|SNE|SOR|SUEQ|SULE|SULT|SUN|SUNE>.<D|S>. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Cc: Douglas Leung <douglas.leung@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Petar Jovanovic <petar.jovanovic@imgtec.com> Cc: Raghu Gandham <raghu.gandham@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17140/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: <MADDF|MSUBF>.D: Fix accuracy (64-bit case)Douglas Leung2017-08-291-39/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement fused multiply-add with correct accuracy. Fused multiply-add operation has better accuracy than respective sequential execution of multiply and add operations applied on the same inputs. This is because accuracy errors accumulate in latter case. This patch implements fused multiply-add with the same accuracy as it is implemented in hardware, using 128-bit intermediate calculations. One test case example (raw bits) that this patch fixes: MADDF.D fd,fs,ft: fd = 0x00000ca000000000 fs = ft = 0x3f40624dd2f1a9fc Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction") Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction") Signed-off-by: Douglas Leung <douglas.leung@imgtec.com> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Cc: Douglas Leung <douglas.leung@imgtec.com> Cc: Bo Hu <bohu@google.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jin Qian <jinqian@google.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Petar Jovanovic <petar.jovanovic@imgtec.com> Cc: Raghu Gandham <raghu.gandham@imgtec.com> Cc: <stable@vger.kernel.org> # 4.7+ Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/16891/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: <MADDF|MSUBF>.S: Fix accuracy (32-bit case)Douglas Leung2017-08-292-70/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement fused multiply-add with correct accuracy. Fused multiply-add operation has better accuracy than respective sequential execution of multiply and add operations applied on the same inputs. This is because accuracy errors accumulate in latter case. This patch implements fused multiply-add with the same accuracy as it is implemented in hardware, using 64-bit intermediate calculations. One test case example (raw bits) that this patch fixes: MADDF.S fd,fs,ft: fd = 0x22575225 fs = ft = 0x3727c5ac Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction") Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction") Signed-off-by: Douglas Leung <douglas.leung@imgtec.com> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Cc: Douglas Leung <douglas.leung@imgtec.com> Cc: Bo Hu <bohu@google.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jin Qian <jinqian@google.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Petar Jovanovic <petar.jovanovic@imgtec.com> Cc: Raghu Gandham <raghu.gandham@imgtec.com> Cc: <stable@vger.kernel.org> # 4.7+ Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/16890/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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