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* Documentation: x86: fix some typosJames Morse2019-06-201-5/+5
| | | | | | | These are all obvious typos. Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
* Documentation: x86: Clarify MBA takes MB as referring to mba_scJames Morse2019-06-201-2/+2
| | | | | | | | | | | | "If the MBA is specified in MB then user can enter the max b/w in MB" is a tautology. How can the user know if the schemata takes a percentage or a MB/s value? This is referring to whether the software controller is interpreting the schemata's value. Make this clear. Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
* Documentation: x86: Remove cdpl2 unspported statement and fix capitalisationJames Morse2019-06-201-4/+10
| | | | | | | | | | | | "L2 cache does not support code and data prioritization". This isn't true, elsewhere the document says it can be enabled with the cdpl2 mount option. While we're here, these sample strings have lower-case code/data, which isn't how the kernel exports them. Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
* Documentation: x86: Contiguous cbm isn't all X86James Morse2019-06-201-1/+1
| | | | | | | | | | | | | Since commit 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature") resctrl has supported non-contiguous cache bit masks. The interface for this is currently try-it-and-see. Update the documentation to say Intel CPUs have this requirement, instead of X86. Cc: Babu Moger <Babu.Moger@amd.com> Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
* Documentation: x86: convert resctrl_ui.txt to reSTChangbin Du2019-05-081-0/+1191
This converts the plain text documentation to reStructuredText format and add it to Sphinx TOC tree. No essential content change. Signed-off-by: Changbin Du <changbin.du@gmail.com> Reviewed-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net>