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* ARM: dts: aspeed: Add HACE device controller nodeNeal Liu2022-08-261-0/+8
| | | | | | | | | Add hace node to device tree for AST2500/AST2600. Signed-off-by: Neal Liu <neal_liu@aspeedtech.com> Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Reviewed-by: Dhananjay Phadke <dphadke@linux.microsoft.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* ARM: dts: aspeed: Enable Dual SPI RX transfersCédric Le Goater2022-05-191-0/+7
| | | | | | | | | | | | All these controllers support at least Dual SPI. Update the DTs. Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-10-clg@kaod.org Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllersCédric Le Goater2022-05-191-6/+3
| | | | | | | | | | | | | This is compatible with the current driver and addresses issues when running 'make dt_binding_check'. Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Tested-by: Joel Stanley <joel@jms.id.au> Tested-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20220509175616.1089346-2-clg@kaod.org Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add PECI controller nodesIwona Winiarska2022-02-091-0/+11
| | | | | | | | | | | | Add PECI controller nodes with all required information. Co-developed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com> Link: https://lore.kernel.org/r/20220208153639.255278-4-iwona.winiarska@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: dts: aspeed: add LCLK setting into LPC KCS nodesJae Hyun Yoo2021-12-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | If LPC KCS driver is registered ahead of lpc-ctrl module, LPC KCS hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property setting into LPC KCS node as one of required properties to enable the LCLK by the LPC KCS driver. Note: dtbs should be re-compiled after applying this change since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20211108190200.290957-5-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: add LCLK setting into LPC IBT nodeJae Hyun Yoo2021-12-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | If LPC BT driver is registered ahead of lpc-ctrl module, LPC BT hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property setting into LPC IBT node as one of required properties to enable the LCLK by the LPC IBT driver. Note: dtbs should be re-compiled after applying this change since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20211108190200.290957-2-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add uart routing to device treeChia-Wei Wang2021-10-211-0/+6
| | | | | | | | | | Add LPC uart routing to the device tree for Aspeed SoCs. Signed-off-by: Oskar Senft <osk@google.com> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Tested-by: Lei YU <yulei.sh@bytedance.com> Link: https://lore.kernel.org/r/20210927023053.6728-6-chiawei_wang@aspeedtech.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: Remove ngpios from sgpio node.Steven Lee2021-08-031-1/+0
| | | | | | | | | | Remove ngpios property from sgpio node as it should be defined in the platform dts. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210712100317.23298-5-steven_lee@aspeedtech.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: Add SCU phandle to GFX nodeJoel Stanley2021-06-041-0/+1
| | | | | | | | In v5.13 the DRM driver gained support for using a phandle to the SCU, instead of matching on the scu compatible. Link: https://lore.kernel.org/r/20210603064536.165297-1-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: Remove LPC BMC and Host partitionsChia-Wei, Wang2021-04-091-77/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The LPC controller has no concept of the BMC and the Host partitions. A concrete instance is that the HICRB[5:4] are for the I/O port address configurtaion of KCS channel 1/2. However, the KCS driver cannot access HICRB for channel 1/2 initialization via syscon regmap interface due to the parition boundary. (i.e. offset 80h) In addition, for the HW design backward compatibility, a newly added HW control bit could be located at any reserved one over the LPC addressing space. Thereby, this patch removes the lpc-bmc and lpc-host child node and thus the LPC partitioning. Note that this change requires the synchronization between device tree change and the driver change. To prevent the misuse of old devicetrees with new drivers, or vice versa, the v2 compatible strings are adopted for the LPC device as listed: "aspeed,ast2400-lpc-v2" "aspeed,ast2500-lpc-v2" "aspeed,ast2600-lpc-v2" Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-2-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add LCLK to lpc-snoopJohn Wang2021-02-091-0/+1
| | | | | | | Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20201202051634.490-2-wangzhiqiang.bj@bytedance.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* Merge tag 'aspeed-5.11-soc' of ↵Arnd Bergmann2020-11-301-0/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into arm/drivers ASPEED soc driver updates for 5.11 New drivers: - SoC info driver to expose revision information New features: - AST2600 support for the LPC control driver. This includes setting the LPC2AHB bridge up in a backwards compatible manner. Cleanups: - LPC control - Kconfig - Bindings updates for AST2600 strings * tag 'aspeed-5.11-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: soc: aspeed: Enable drivers with ARCH_ASPEED soc: aspeed: Fix a reference leak in aspeed_socinfo_init() soc: aspeed: remove unneeded semicolon soc: aspeed-lpc-ctrl: Fix driver name soc: aspeed-lpc-ctrl: Fix whitespace soc: aspeed-lpc-ctrl: LPC to AHB mapping on ast2600 soc: aspeed-lpc-ctrl: Fail probe of lpc-ctrl if reserved memory is not aligned soc: aspeed: lpc: Add AST2600 compatible strings dt-bindings: aspeed-lpc: Add AST2600 compatible strings ARM: dts: aspeed: Add silicon id node soc: aspeed: Add soc info driver dt-bindings: aspeed: Add silicon id node to SCU soc: aspeed: Improve kconfig Link: https://lore.kernel.org/r/CACPK8Xe=9ezhyWRMqVOEQr7SU1YoYfVBGGdGzjmE4SiBr--vJQ@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: dts: aspeed: Add silicon id nodeJoel Stanley2020-09-251-0/+5
| | | | | | | | | | | | | | | | | | This register describes the silicon id and chip unique id. It varies between CPU revisions, but is always part of the SCU. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20200921091644.133107-4-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
* | ARM: aspeed: g5: Do not set sirq polarityJoel Stanley2020-09-091-1/+0
|/ | | | | | | | | | | | | | | | | | | | | | | A feature was added to the aspeed vuart driver to configure the vuart interrupt (sirq) polarity according to the LPC/eSPI strapping register. Systems that depend on a active low behaviour (sirq_polarity set to 0) such as OpenPower boxes also use LPC, so this relationship does not hold. Jeremy confirms that the s2600st which is strapped for eSPI also does not have this relationship. The property was added for a Tyan S7106 system which is not supported in the kernel tree. Should this or other systems wish to use this feature of the driver they should add it to the machine specific device tree. Fixes: c791fc76bc72 ("arm: dts: aspeed: Add vuart aspeed,sirq-polarity-sense...") Signed-off-by: Joel Stanley <joel@jms.id.au> Tested-by: Jeremy Kerr <jk@ozlabs.org> Reviewed-by: Jeremy Kerr <jk@ozlabs.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200812112400.2406734-1-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: ast2500: Update XDMA engine nodeEddie James2020-07-201-2/+3
| | | | | | | | Correct the pcie-device property, and add the Aspeed SCU interrupt controller include. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Change KCS nodes to v2 bindingAndrew Jeffery2020-05-051-12/+12
| | | | | | | | | | | Fixes the following warnings for both g5 and g6 SoCs: arch/arm/boot/dts/aspeed-g5.dtsi:376.19-381.8: Warning (unit_address_vs_reg): /ahb/apb/lpc@1e789000/lpc-bmc@0/kcs1@0: node has a unit name, but no reg property Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: ast2500: Add XDMA EngineEddie James2020-05-051-0/+11
| | | | | | | | Add a node for the XDMA engine with all the necessary information. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: ast2500: Add SCU interrupt controllerEddie James2020-05-051-0/+8
| | | | | | | | Add a node for the interrupt controller provided by the SCU. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: add vhub port and endpoint propertiesTao Ren2020-03-151-0/+2
| | | | | | | | | | Add "aspeed,vhub-downstream-ports" and "aspeed,vhub-generic-endpoints" properties to describe supported number of vhub ports and endpoints. Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Felipe Balbi <balbi@kernel.org>
* ARM: dts: aspeed-g5: Sort LPC child nodes by unit addressAndrew Jeffery2019-12-171-5/+6
| | | | | | | | Lets try to maintain some sort of sanity. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add reg hints to syscon childrenAndrew Jeffery2019-12-171-8/+10
| | | | | | | | | | | Fixes the following warnings: arch/arm/boot/dts/aspeed-g5.dtsi:209.28-226.6: Warning (avoid_unnecessary_addr_size): /ahb/apb/syscon@1e6e2000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property arch/arm/boot/dts/aspeed-g4.dtsi:156.28-172.6: Warning (avoid_unnecessary_addr_size): /ahb/apb/syscon@1e6e2000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Cleanup lpc-ctrl and snoop regsAndrew Jeffery2019-12-171-3/+3
| | | | | | | | | | Fix the following warning: arch/arm/boot/dts/aspeed-g5.dtsi:409.27-414.8: Warning (unique_unit_address): /ahb/apb/lpc@1e789000/lpc-host@80/lpc-ctrl@0: duplicate unit-address (also used in node /ahb/apb/lpc@1e789000/lpc-host@80/lpc-snoop@0) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: Use recommended generic node name for SDMCAndrew Jeffery2019-12-171-1/+1
| | | | | | | | | | | The EDAC is a sub-function of the SDRAM Memory Controller. Rename the node to the appropriate generic node name. Cc: Stefan M Schaeckeler <sschaeck@cisco.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Stefan Schaeckeler <sschaeck@cisco.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: Move EDAC node to APBAndrew Jeffery2019-12-171-7/+7
| | | | | | | | | | | Previously the register interface was not attached to any internal bus, which is not correct - it lives on the APB. Cc: Stefan M Schaeckeler <sschaeck@cisco.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Stefan Schaeckeler <sschaeck@cisco.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2019-12-051-2/+24
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM Device-tree updates from Olof Johansson: "As always, the bulk of updates. Some of the news this cycle: New SoC descriptions: - Broadcom BCM2711 - Amlogic Meson A1 and G12 - Freescale S32V234 - Marvell Armada AP807/AP807-quad and CP115 - Realtek RTD1293 and RTD1296 - Rockchip RK3308 New boards and platforms: - Allwinner: NanoPi Duo2 - Amlogic: Ugoos am6 - Atmel at91: Overkiz Kizbox2/4 - Broadcom: RPi4, Luxul XWC-2000 - Marvell: New Espressobin flavor - NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and OPOS6ULDev - Renesas: Salvator-XS - Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits) ARM: dts: logicpd-torpedo: Disable USB Host arm: dts: mt6323: add keys, power-controller, rtc and codec arm64: dts: mt8183: add systimer0 device node dt-bindings: mediatek: update bindings for MT8183 systimer arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board. arm64: dts: rockchip: Add Beelink A1 dt-bindings: ARM: rockchip: Add Beelink A1 arm64: dts: rockchip: Add RK3328 audio pipelines arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports arm64: dts: ti: k3-j721e-main: add USB controller nodes ARM: dts: aspeed-g6: Add timer description ARM: dts: aspeed: ast2600evb: Enable i2c buses ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards dt-bindings: arm: at91: Document Kizbox2-2 board binding arm64: dts: meson-gx: fix i2c compatible arm64: dts: meson-gx: cec node should be disabled by default arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible arm64: dts: meson-gxm: fix gpu irq order arm64: dts: meson-g12a: fix gpu irq order ...
| * ARM: dts: aspeed-g5: Add SGPIO descriptionHongwei Zhang2019-11-011-1/+16
| | | | | | | | | | | | | | Add SGPIO node to the ASPEED AST2500 device tree. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: Add "spi-max-frequency" propertyCédric Le Goater2019-11-011-0/+7
| | | | | | | | | | | | | | | | | | Keep the FMC controller chips at a safe 50 MHz rate and use 100 MHz for the PNOR on the machines using a AST2500 SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: aspeed: Migrate away from aspeed, g[45].* compatiblesAndrew Jeffery2019-11-011-1/+1
| | | | | | | | | | | | | | | | Use the SoC-specific compatible strings instead. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
* | arm: dts: aspeed: Add vuart aspeed,sirq-polarity-sense to aspeed-g5.dtsiOskar Senft2019-10-041-0/+1
|/ | | | | | | | Enable auto-configuration of VUART SIRQ polarity on AST2500. Signed-off-by: Oskar Senft <osk@google.com> Link: https://lore.kernel.org/r/20190905144130.220713-3-osk@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: dts: aspeed-g5: Fixe gpio-ranges upper limitOscar A Perez2019-09-041-1/+1
| | | | | | | | | | | | | | According to the AST2500/AST2520 specs, these SoCs support up to 228 GPIO pins. However, 'gpio-ranges' value in 'aspeed-g5.dtsi' file is currently setting the upper limit to 220 which isn't allowing access to all their GPIOs. The correct upper limit value is 232 (actual number is 228 plus a 4-GPIO hole in GPIOAB). Without this patch, GPIOs AC5 and AC6 do not work correctly on a AST2500 BMC running Linux Kernel v4.19 Fixes: 2039f90d136c ("ARM: dts: aspeed-g5: Add gpio controller to devicetree") Signed-off-by: Oscar A Perez <linux@neuralgames.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Describe SD controllersAndrew Jeffery2019-08-211-0/+28
| | | | | | | | | The AST2400 and AST2500 both share the same SD controller, at the same location in the physical address space and the same hardware interrupt, with the same clock configurations. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add SGPM pinmuxHongwei Zhang2019-07-231-0/+5
| | | | | | | | | Add SGPM pinmux to ast2500-pinctrl function and group, to prepare for supporting SGPIO in AST2500 SoC. Signed-off-by: Hongwei Zhang <hongweiz@ami.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add aspeed-p2a-ctrl nodePatrick Venture2019-05-241-0/+5
| | | | | | | | | Add a node for the aspeed-p2a-ctrl module. This node, when enabled will disable the PCI-to-AHB bridge and then allow control of this bridge via ioctls, and access via mmap. Signed-off-by: Patrick Venture <venture@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Rename flash-controller nodesJoel Stanley2019-05-241-3/+3
| | | | | | | | | | | | | The device tree compiler has started spitting out warnings about these names, insisting they be called 'spi': ../arch/arm/boot/dts/aspeed-g5.dtsi:108.35-128.5: Warning (spi_bus_bridge): /ahb/flash-controller@1e631000: node name for SPI buses should be 'spi' Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add RTC nodeJoel Stanley2019-04-051-0/+6
| | | | | | The ASPEED ast2400 and ast2500 both contain an on board RTC device. Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: Add video engineEddie James2019-04-051-0/+10
| | | | | | | Add a node to describe the video engine on the AST2500. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed-g5: Add resets and clocks to GFX nodeJoel Stanley2019-04-051-0/+4
| | | | | | | | | The ast2500 has a reset for the CRT device that must be deasserted before it can be used. Similarly it has a clock gate for a clock called D1CLK that must be set to running. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* Merge tag 'edac_for_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bpLinus Torvalds2019-03-081-0/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull EDAC updates from Borislav Petkov: - A new EDAC AST 2500 SoC driver (Stefan M Schaeckeler) - New i10nm EDAC driver for Intel 10nm CPUs (Qiuxu Zhuo and Tony Luck) - Altera SDRAM functionality carveout for separate enablement of RAS and SDRAM capabilities on some Altera chips. (Thor Thayer) - The usual round of cleanups and fixes And last but not least: recruit James Morse as a reviewer for the ARM side. * tag 'edac_for_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: EDAC/altera: Add separate SDRAM EDAC config EDAC, altera: Add missing of_node_put() EDAC, skx_common: Add code to recognise new compound error code EDAC, i10nm: Fix randconfig builds EDAC, i10nm: Add a driver for Intel 10nm server processors EDAC, skx_edac: Delete duplicated code EDAC, skx_common: Separate common code out from skx_edac EDAC: Do not check return value of debugfs_create() functions EDAC: Add James Morse as a reviewer dt-bindings, EDAC: Add Aspeed AST2500 EDAC, aspeed: Add an Aspeed AST2500 EDAC driver
| * EDAC, aspeed: Add an Aspeed AST2500 EDAC driverStefan M Schaeckeler2019-01-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Aspeed AST2500 SoC. Signed-off-by: Stefan M Schaeckeler <sschaeck@cisco.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Joel Stanley <joel@jms.id.au> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-aspeed@lists.ozlabs.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: https://lkml.kernel.org/r/1547743097-5236-2-git-send-email-schaecsn@gmx.net
* | ARM: dts: aspeed: Add KCS support for LPC BMCVijay Khemka2019-01-171-1/+32
| | | | | | | | | | | | | | | | | | This adds the description of the four Keyboard Controller Style (KCS) IPMI communication channels present in the ASPEED BMC. They are disabled by default. Signed-off-by: Vijay Khemka <vijaykhemka@fb.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* | ARM: dts: aspeed: Add #interrupt-cells property to gpio controllersMark Walton2019-01-171-0/+1
|/ | | | | | | | | | Allows the GPIO controller to be used as an interrupt parent. of_irq_find_parent() skips interrupt controller nodes that do not have the #interrupt-cells property. Signed-off-by: Mark Walton <mark.walton@serialtek.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Fix I2C bus warningsRob Herring2018-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | dtc has new checks for I2C buses. The ASpeed dts files have a node named 'i2c' which causes a false positive warning. As the node is a 'simple-bus', correct the node name to be 'bus' to fix the warnings. arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-romulus.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-ast2500-evb.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-opp-zaius.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dtb: Warning (i2c_bus_bridge): /ahb/apb/i2c@1e78a000: incorrect #size-cells for I2C bus Cc: Joel Stanley <joel@jms.id.au> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: linux-aspeed@lists.ozlabs.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add coprocessor interrupt controllerBenjamin Herrenschmidt2018-07-251-1/+8
| | | | | | | | | Add a node for the CVIC (the coprocessor interrupt controller) and add a label to the SRAM node so it can be referenced from the board device-tree file. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Use 24MHz fixed clock for pwmLei YU2018-07-181-1/+1
| | | | | | | | | The aspeed pwm driver always sets the clock source to 24MHz, specify the fixed clock in device tree to make sure the driver is using the correct clock frequency to calculate the fan speed. Signed-off-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add G5 USB Virtual HubBenjamin Herrenschmidt2018-07-161-0/+15
| | | | | | | | | | | This adds the (disabled by default) device node for the Aspeed virtual hub,a long with clocks and pinmux. This also adds the missing pinmux definition for it (the kernel driver already knows about it). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add G5 USB host pinmuxBenjamin Herrenschmidt2018-07-161-0/+8
| | | | | | | | | | | | Set the default pinmux for EHCIs so boards don't have to do it an document why it is not set for UHCI. Remove the properties from the AST2500 EVB board which are now redundant Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Fix hwrng register addressJoel Stanley2018-06-021-2/+2
| | | | | | | | | | The register address should be the full address of the rng, not the offset from the start of the SCU. Fixes: 5daa8212c08e ("ARM: dts: aspeed: Describe random number device") Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: dts: Add Aspeed SoC USB controllers to device-treeBenjamin Herrenschmidt2018-05-251-0/+40
| | | | | | | | | | | | | | | | | | | This adds the USB controllers to the DT template of the AST24xx and AST25xx SoCs. This patch doesn't enable them by default on any board specific .dts yet. This will be done when we have the necessary clock/reset and pinmux support. In the meantime though, this will work if u-boot configures things properly. For the AST2400 I only added pinmux definition for port 1 which is dual USB1/USB2. There are additional USB1 only ports that might require more work but I don't have HW to test at hand so I'm leaving that to whoever cares. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Describe random number deviceJoel Stanley2018-04-301-0/+7
| | | | | | | | | | | | | | | | | | | | | | There is a random number generator that updates a register in the SCU every second. This is compatible with the timeriomem rng driver in the kernel. From the timeriomem_rng bindings: quality: estimated number of bits of true entropy per 1024 bits read from the rng. Defaults to zero which causes the kernel's default quality to be used instead. Note that the default quality is usually zero which disables using this rng to automatically fill the kernel's entropy pool. As to the recommended value for us to use: Rick Altherr <raltherr@google.com> wrote: > Quality is #bit of entropy per 1000 bits read. 100 is a > conservative value that was suggested by those in the know. Signed-off-by: Joel Stanley <joel@jms.id.au>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2018-04-051-4/+21
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree updates from Arnd Bergmann: "This is the usual set of changes for device trees, with over 700 non-merged changesets. There is an ongoing set of dtc warning fixes and the usual bugfixes, cleanups and added device support. The most interesting bit as usual is support for new machines listed below: - The Allwinner H6 makes its debut with the Pine-H64 board, and we get two new machines based on its older siblings: the H5 based OrangePi Zero+ and the A64 based Teres-I Laptop from Olimex. On the 32-bit side, we add The Olimex som204 based on Allwinner A20, and the Banana Pi M2 Zero development board (based on H2). - NVIDIA adds support for Tegra194 aka "Xavier", plus their p2972 development board and p2888 CPU module. - The Nuvoton npcm750 is a BMC that was newly added, for now we only support running on the evaluation board. - STmicroelectronics stm32 gains support for the stm32mp157c and two evaluation boards. - The Toradex Colibri board family grows a few members based on the i.MX6ULL variant. - The Advantec DMS-BA16 is a Qseven module using the NXP i.MX6 family of chips. - The Phytec phyBOARD Mira is a family of industrial boards based on i.MX6. For now, four models get added. - TI am335x based PDU-001 is an industrial embedded machine used for traffic monitoring - The Aspeed platform now supports running on the BMC on the Qualcomm Centriq 2400 server - Samsung Exynos4 based Galaxy S3 is a family of mobile phones Qualcomm msm8974 based Galaxy S5 is a rather different phone made by the same company. - The Xilinx Zynq and ZynqMP platforms now gained a lot of dts file for the various boards made by Xilinx themselves, as well as the Digilent Zybo Z7. - The ARM Versatile family now supports the "IB2" interface board. - The Renesas H2 based "Stout" and the H3 based Salvator-X are more evaluation boards named after a kind of beer, as most of them are. The r8a77980 (V3H) based "Condor" apparently doesn't follow that tradition. ;-) - ROC-RK3328-CC is a simple developement board from the Libre Computer Project, based on the Rockchips RK3328 SoC - Haiku is another development board plus Qseven module based on Rockchips RK3368 and made by Theobroma Systems" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (701 commits) arm: dts: modify Nuvoton NPCM7xx device tree structure arm: dts: modify Makefile NPCM750 configuration name arm: dts: modify clock binding in NPCM750 device tree arm: dts: modify timer register size in NPCM750 device tree arm: dts: modify UART compatible name in NPCM750 device tree arm: dts: add watchdog device to NPCM750 device tree arm64: dts: uniphier: add ethernet node for PXs3 ARM: dts: uniphier: add pinctrl groups of ethernet for second instance arm: dts: kirkwood*.dts: use SPDX-License-Identifier for board using GPL-2.0+ arm: dts: kirkwood*.dts: use SPDX-License-Identifier for boards using GPL-2.0+/MIT arm: dts: kirkwood*.dts: use SPDX-License-Identifier for boards using GPL-2.0 arm: dts: armada-385-turris-omnia: use SPDX-License-Identifier arm: dts: armada-385-db-ap: use SPDX-License-Identifier arm: dts: armada-388-rd: use SPDX-License-Identifier arm: dts: armada-xp-db-xc3-24g4xg: use SPDX-License-Identifier arm: dts: armada-xp-db-dxbc2: use SPDX-License-Identifier arm: dts: armada-370-db: use SPDX-License-Identifier arm: dts: armada-*.dts: use SPDX-License-Identifier for most of the Armada based board arm: dts: armada-xp-98dx: use SPDX-License-Identifier for prestara 98d SoCs arm: dts: armada-*.dtsi: use SPDX-License-Identifier for most of the Armada SoCs ...
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-06 18:55:55 +0000