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* ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h headerChen-Yu Tsai2017-03-271-1/+0
| | | | | | | | | | | | | | | | | All dts files for the sunxi platform have been switched to the generic pinconf bindings. As a result, the sunxi specific pinctrl macros are no longer used. Remove the #include entry with the following command: sed --follow-symlinks -i -e '/pinctrl\/sun4i-a10.h/D' \ arch/arm/boot/dts/sun?i*.* arch/arm/boot/dts/sun9i-a80.dtsi was then edited to remove the extra empty line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'sunxi-dt-for-4.11' of ↵Arnd Bergmann2017-02-071-0/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt Pull "Allwinner DT changes for 4.11" from Maxime Ripard: The usual chunk of DT changes, most notably: - Support for the H2+ and the V3s - CPUFreq support for the A33 - SPDIF support for the A31 and H3 - New boards: Beelink X2, Lichee Pi One, Lichee Pi Zero, Orange Pi Zero * tag 'sunxi-dt-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (42 commits) ARM: dts: sun8i-h3: Add SPDIF to the Beelink X2 ARM: dts: sun8i-h3: Add the SPDIF block to the H3 ARM: dts: sun8i-h3: Add SPDIF TX pin to the H3 ARM: dts: sun8i-h3: Add dts for the Beelink X2 STB ARM: sun8i: sina33: Enable display ARM: sun8i: a23/a33: Add the oscillators accuracy ARM: sun8i: a23/a33: Enable the real LOSC and use it ARM: dts: sunxi: add support for Lichee Pi Zero board ARM: dts: sunxi: add dtsi file for V3s SoC ARM: dts: sun6i: sina31s: Enable USB OTG controller in peripheral mode ARM: dts: sun8i: reference-design: use AXP223 DTSI ARM: dts: sun8i: parrot: use AXP223 DTSI ARM: dts: sun8i: sina33: use AXP223 DTSI ARM: dts: sun8i: a33-olinuxino: use AXP223 DTSI ARM: dts: add DTSI for AXP223 dt-bindings: power: axp20x-usb: add axp223 compatible ARM: dts: sun7i: Add wifi dt node on Banana Pro ARM: dts: sun6i: Add SPDIF to the Mele I7 devicetree: bindings: Add vendor prefix for Shenzhen Xunlong Software ARM: dts: sun8i-h3: orange-pi-pc: Enable audio codec ...
| * ARM: dts: sunxi: Add num-cs for A20 spi nodesEmmanuel Vadot2017-01-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | The spi0 controller on the A20 have up to 4 CS (Chip Select) while the others three only have 1. Add the num-cs property to each node. The current driver doesn't read this property but this is useful for downstream user of DTS (FreeBSD for example). Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: dts: sunxi: Explicitly enable pull-ups for MMC pinsChen-Yu Tsai2017-01-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the past, all the MMC pins had allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; which was actually a no-op. We were relying on U-boot to set the bias pull up for us. These properties were removed as part of the fix up to actually support no bias on the pins. During the transition some boards experienced regular MMC time-outs during normal operation, while others completely failed to initialize the SD card. Given that MMC starts in open-drain mode and the pull-ups are required, it's best to enable it for all the pin settings. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: DTS: Fix register map for virt-capable GICMarc Zyngier2017-02-071-2/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: sunxi: Convert pinctrl nodes to generic bindingsMaxime Ripard2016-12-261-102/+102
| | | | | | | | Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: Remove useless allwinner,pull propertyMaxime Ripard2016-12-261-37/+0
| | | | | | | | | | | | The allwinner,pull property set to NO_PULL was really considered our default (and wasn't even changing the default value in the code). Remove these properties to make it obvious that we do not set anything in such a case. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: Remove useless allwinner,drive propertyMaxime Ripard2016-12-261-36/+0
| | | | | | | | | The allwinner,drive property set to 10mA was really considered as our default. Remove all those properties entirely to make that obvious. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: Add the missing clocks to the pinctrl nodesMaxime Ripard2016-11-221-1/+2
| | | | | | | | | The pin controllers also use the two oscillators for debouncing. Add them to the DTs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sunxi: Use new sun7i-a20-mmc compatible on sun7i and newerHans de Goede2016-09-261-4/+4
| | | | | | | | | Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i and newer. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* ARM: sun7i: Add DAI nodesMaxime Ripard2016-07-041-0/+39
| | | | | | Add the new DAI blocks to the device tree. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun7i: Add mod1 clock nodesEmilio López2016-07-041-2/+46
| | | | | | | | This commit adds all the mod1 clocks available on A20 to its device tree. This list was created by looking at the A20 user manual. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add NFC node to Allwinner A20 SoCBoris Brezillon2016-07-041-0/+13
| | | | | | | | Add NAND Flash controller node definition to the A20 SoC. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Re-order pinctrl nodes alphabeticallyAleksei Mamlin2016-07-041-142/+142
| | | | | | | No functional change. Re-order sun7i pinctrl nodes alphabetically. Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: HDMI and the tv-encoder use tcon ch1 not ch0Hans de Goede2016-07-041-4/+6
| | | | | | | | | | | Update the simplefb nodes for hdmi / tv-encoder out to point to tcon0_ch1 instead of tcon0_ch0 as tcon clock. While at it fix the clocks lines being longer than 80 chars. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun7i: A20: Add display and TCON clocksPriit Laes2016-07-041-7/+81
| | | | | | | | Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Fix pll3x2 and pll7x2 not having a parent clockHans de Goede2016-06-291-0/+2
| | | | | | | | | Fix pll3x2 and pll7x2 not having a parent clock, specifically this fixes the kernel turning of pll3 while simplefb is using it when uboot has configured things to use pll3x2 as lcd ch clk parent. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Add pll3 to simplefb nodes clocks listsHans de Goede2016-06-221-5/+6
| | | | | | | | | | | Now that we've a clock node describing pll3 we must add it to the simplefb nodes clocks lists to avoid it getting turned off when simplefb is used. This fixes the screen going black when using simplefb. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun7i: dt: Add pll3 and pll7 clocksPriit Laes2016-05-081-0/+41
| | | | | | | Enable pll3 and pll7 clocks that are needed by display clocks. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun7i: dt: Enable dram gate 5 (tve0 clock) for simplefb TV outputPriit Laes2016-03-271-2/+3
| | | | | | | | | | | Seems like dram_gate 5 was forgotten when DRAM gating driver was added. Add it. Cc: stable@vger.kernel.org Fixes: 0b4bf5a5200b (ARM: dts: sun7i: Add DRAM gates) Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add the SPDIF block to the A20Marcus Cooper2016-03-271-0/+13
| | | | | | | Add the SPDIF transceiver controller block to the A20 dtsi. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add the SPDIF clk to the A20Marcus Cooper2016-03-271-0/+11
| | | | | | | Add the SPDIF clock to the A20 dtsi. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add SPDIF TX pin to the A20Marcus Cooper2016-03-271-0/+7
| | | | | | | Add the SPDIF TX pin to the A20 dtsi. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add VE (Video Engine) module clock nodeChen-Yu Tsai2015-12-081-0/+9
| | | | | | | | The video engine has its own module clock, which also includes a reset control for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add DRAM gatesChen-Yu Tsai2015-12-071-3/+29
| | | | | | | | | The DRAM gates controls direct memory access for some peripherals. These peripherals include the display pipeline, so add the required gates to the simplefb nodes as well. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun7i: Add sunxi codec device nodeEmilio López2015-10-211-0/+13
| | | | | | | | | | The A20 SoC includes the Allwinner audio codec, capable of both 24-bit playback and capture. This commit adds a device node for it. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun7i: Add audio codec clockMaxime Ripard2015-10-211-0/+9
| | | | | | | | The audio codec functional clock is a child of PLL2 and is used to control the audio rate, enable it in the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun7i: Add audio PLLMaxime Ripard2015-10-211-0/+9
| | | | | | | | The A20 uses the PLL2 as the audio PLL, which is the parent of all the other audio clocks in the system (i2s, codec, etc.). Add it to the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun7i: Add keypad clk nodeYassin Jaffer2015-09-271-0/+8
| | | | | | | This patch add support to the keypad clock on sun7i Signed-off-by: Yassin Jaffer <yassinjaffer@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Raise minimum CPU voltage for sun7i-a20 to meet SoC ↵Timo Sigurdsson2015-09-131-1/+1
| | | | | | | | | | | | | | | | specifications sun7i-a20.dtsi contains a cpufreq operating point at 0.9 volts. The minimum CPU voltage for the Allwinner A20 SoC, however, is 1.0 volts. Thus, raise the voltage for the lowest operating point to 1.0 volts in order to stay within the SoC specifications. It is an undervolted setting that isn't stable across all SoCs and boards out there. Cc: <stable@vger.kernel.org> # v4.0+ Fixes: d96b7161916f ("ARM: dts: sun7i: Add cpu clock reference and operating points to dtsi") Signed-off-by: Timo Sigurdsson <public_timo.s@silentcreek.de> Acked-by: Iain Paton <ipaton0@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2015-09-011-2/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Ladies and gentlemen, we proudly announce to you the latest branch of ARM device tree contents for the mainline kernel. Come and see, come and see! No less than twentythree thousand lines of additions! Just imagine the joy you will have of using your mainline kernel on newly supported hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or UniPhier hardware! For those of you feeling less adventurous, added hardware support on platforms such as TI DM814x and Gumstix Overo platforms might be more of your liking. We've got something for everyone here! Ahem. Cough. So, anyway... This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - cleanups for Renesas shmobile platforms - lots of added devices on LPC18xx - lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits) ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller. ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes ARM: dts: rockchip: correct regulator power states for suspend ARM: dts: rockchip: correct regulator PM properties ARM: dts: vexpress: Use assigned-clock-parents for sp810 pinctrl: tegra: Only set the gpio range if needed arm: boot: dts: am4372: add ARM timers and SCU nodes ARM: dts: AM4372: Add the am4372-rtc compatible string ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain ...
| * ARM: sunxi: dt: Convert users to the PIO interrupts bindingMaxime Ripard2015-07-281-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current DTs were setting the cell size to 2, but used the default xlate function that was assuming an interrupt cell size of 1, leading to the second part of the cell (the flags) being ignored, while we were having an inconsistent binding between the interrupts and gpio (that could also be used as interrupts). That "binding" doesn't work either with newer SoCs that have multiple irq banks. Now that we fixed the pinctrl driver to handle this like it should always have been handled, convert the DT users, and while we're at it, remove the size-cells property of PIO that is completely useless. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: dts: sun7i: Add USB Dual Role ControllerRoman Byshko2015-07-061-0/+13
| | | | | | | | | | | | | | Add a node for the otg/drc usb controller to sun7i-a20.dtsi Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Linus Torvalds2015-08-311-0/+8
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull crypto updates from Herbert Xu: "Here is the crypto update for 4.3: API: - the AEAD interface transition is now complete. - add top-level skcipher interface. Drivers: - x86-64 acceleration for chacha20/poly1305. - add sunxi-ss Allwinner Security System crypto accelerator. - add RSA algorithm to qat driver. - add SRIOV support to qat driver. - add LS1021A support to caam. - add i.MX6 support to caam" * git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (163 commits) crypto: algif_aead - fix for multiple operations on AF_ALG sockets crypto: qat - enable legacy VFs MPI: Fix mpi_read_buffer crypto: qat - silence a static checker warning crypto: vmx - Fixing opcode issue crypto: caam - Use the preferred style for memory allocations crypto: caam - Propagate the real error code in caam_probe crypto: caam - Fix the error handling in caam_probe crypto: caam - fix writing to JQCR_MS when using service interface crypto: hash - Add AHASH_REQUEST_ON_STACK crypto: testmgr - Use new skcipher interface crypto: skcipher - Add top-level skcipher interface crypto: cmac - allow usage in FIPS mode crypto: sahara - Use dmam_alloc_coherent crypto: caam - Add support for LS1021A crypto: qat - Don't move data inside output buffer crypto: vmx - Fixing GHASH Key issue on little endian crypto: vmx - Fixing AES-CTR counter bug crypto: null - Add missing Kconfig tristate for NULL2 crypto: nx - Add forward declaration for struct crypto_aead ...
| * | ARM: sun7i: dt: Add Security System to A20 SoC DTSLABBE Corentin2015-07-201-0/+8
| |/ | | | | | | | | | | | | | | | | | | | | The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG algorithms. It could be found on many Allwinner SoC. This patch enable the Security System on the Allwinner A20 SoC Device-tree. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* / ARM: sun7i: Add clock indicesMaxime Ripard2015-08-121-0/+23
|/ | | | | | | | The A20 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* ARM: dts: sun7i: Add A20 SRAM and SRAM controllerMaxime Ripard2015-06-011-0/+37
| | | | | | | | | | | | | The A20 has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Add the SRAM controller, the SRAM that it drives and the section that can be used by the various devices. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com>
* ARM: dts: sunxi: Revert SRAM controller drivers patchesMaxime Ripard2015-06-011-34/+0
| | | | | | | | | | | | This patch reverts commit ccb4ada2f193 ("ARM: dts: sun7i: Add A20 SRAM and SRAM controller"), commit e6f51e4bd2a5 ("ARM: dts: sun5i: Add A13 and A10s SRAM and SRAM controller") and commit 6d92b80f356f ("ARM: dts: sun4i: Add A10 SRAM and SRAM controller"). The bindings have been changed in the SRAM driver, and we need to change the DT accordingly. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add uart4_pins_b definitionMichael Ring2015-06-011-0/+7
| | | | | | | | | Some boards (e.g. the BananaPro) use alternative pins for uart4, add a pinmux entry for these. Signed-off-by: Michael Ring <mail@michael-ring.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dt: Split the SPI pinctrl groupsMaxime Ripard2015-05-101-4/+39
| | | | | | | | | | | | | | | | | | | The pinctrl groups for SPI until now were also adding the chip selects in the SPI pinctrl group. This was causing a few issues, since a board was forced to use a random number of chipselects, even though it might use one of these chip selects for another pin. The number of chipselects defined was also not the same from one group to another because of different needs at the time these groups have been introduced, resulting in no clear view from the board DTS on what exactly is being muxed, which even might change in the future. Solve this by creating different pinctrl groups for the chipselects and the standard SPI pins (CLK, MOSI and MISO) so that we fix both issues. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dt: Fix whitespace errorsMaxime Ripard2015-05-101-9/+9
| | | | | | | | | A few lines (probably copy pasted) have an indentation mixing tabs and spaces that triggers a checkpatch warning. Fix those, and while we're at it, fix the space-indented sections. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: DT: Fix lines over 80 charactersMaxime Ripard2015-05-101-14/+27
| | | | | | | | | A few lines in our DTSIs are over the 80 characters limit, making checkpatch complain about that. If possible (and relevant), wrap these lines to 80 characters. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dt: Remove the FSF addressMaxime Ripard2015-05-101-5/+0
| | | | | | | | | | The FSF address triggers a warning on checkpatch, saying that the FSF license is already present in the Linux source code, and that it has already changed in the past. Remove it from our DT, as suggested. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dts: split IR pins for A10 and A20Marcus Cooper2015-05-021-4/+18
| | | | | | | | | | Currently none of the target boards nor the driver supports IR TX. However this pin is used in a few instances as a GPIO. Split the pin ctrl descriptions so that only the IR RX is configured to be used. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Update ahb clocks for sun5i and sun7iChen-Yu Tsai2015-04-271-3/+10
| | | | | | | | | | | | | | | The clock driver now supports a muxable ahb clock. Update the dtsi with the proper compatible and add the new parent clocks. This also adds the new pll6/4 output for pll6 on sun7i-a20. The output is not used on sun4/5i. Also use assigned-clocks to reparent ahb to pll6. We want ahb to have a stable, non-changing clock rate. cpu/axi clock rate changes as a result of newly added cpufreq support. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add A20 SRAM and SRAM controllerMaxime Ripard2015-04-271-0/+34
| | | | | | | | | | | | | | The A20 has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Since most of the time these SRAM won't be accessible by the CPU, we can't use the mmio-sram driver and compatible. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [hdegoede@redhat.com: Do not change soc node name, change compatible to sun4i-a10-sram-controller to match the driver change] Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodesHans de Goede2015-04-271-0/+8
| | | | | | | | | | | | | | Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Adjust touchscreen compatible for sun5i and laterHans de Goede2015-04-271-1/+1
| | | | | | | | | | The touchscreen controller in the A13 and later has a different temperature curve than the one in the original A10, change the compatible for the A13 and later so that the kernel will use the correct curve. Reported-by: Tong Zhang <lovewilliam@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Remove overclocked/overvoltaged OPPChen-Yu Tsai2015-03-241-2/+1
| | | | | | | | | | | | | | Without proper regulator support for individual boards, it is dangerous to have overclocked/overvoltaged OPPs in the list. Cpufreq will increase the frequency without the accompanying voltage increase, resulting in an unstable system. Remove them for now. We can revisit them with the new version of OPP bindings, which support boost settings and frequency ranges, among other things. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'clk-for-linus-3.20' of ↵Linus Torvalds2015-02-211-20/+52
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-11 15:23:37 +0000