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* ARM: mach-at91: Setup consistent dma size at boot timeJon Medhurst2011-08-221-0/+2
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Ferre<nicolas.ferre@atmel.com>
* at91: factorize sram initJean-Christophe PLAGNIOL-VILLARD2011-07-281-10/+1
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: move register clocks to soc generic initJean-Christophe PLAGNIOL-VILLARD2011-07-281-3/+1
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: move clock subsystem init to soc generic initJean-Christophe PLAGNIOL-VILLARD2011-07-281-4/+1
| | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: use structure to store the current socJean-Christophe PLAGNIOL-VILLARD2011-07-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | instead of reading the registers everytime the current implementation respect the following constrain: - allow 1 to n soc to be enabled - allow to have a virtual cpu type and subtype - always detect the cpu type and subtype and report it - detect if the soc support is enabled - prepare for sysfs export support - drop soc specific code via compiler when the soc not enabled (via cpu_is_xxx) Today if we read the exid we will have the same value for 9g35 and 9m11 and we will need to check the cidr too with the new implementation we just need to check the soc subtype this will also allow to have specific virtual subtype for rm9200 which the board will have to specify via at91rm9200_set_type(int) as we have no way to detect it. this implementation is inspired by the SH cpu detection support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: factorize at91 interrupts init to socJean-Christophe PLAGNIOL-VILLARD2011-07-281-12/+1
| | | | | | | | they are the same except the default priority Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: introduce commom AT91_BASE_SYSJean-Christophe PLAGNIOL-VILLARD2011-07-281-10/+10
| | | | | | | | | | | | | | | | On all at91 except rm9200 and x40 have the System Controller starts at address 0xffffc000 and has a size of 16KiB. On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting at 0xfffff000 This patch removes the individual definitions of AT91_BASE_SYS and replaces them with a common version at base 0xfffffc000 and size 16KiB and map the same memory space Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: fix udc, ehci and mmc clock device name for cap9/9g45/9rlJean-Christophe PLAGNIOL-VILLARD2011-06-251-5/+5
| | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* at91: switch to CLKDEV_LOOKUPJean-Christophe PLAGNIOL-VILLARD2011-05-251-18/+41
| | | | | | | | | we do not change the clock naming convention so does not need to switch the AVR32 yet Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
* at91: fix map_io init usageJean-Christophe PLAGNIOL-VILLARD2011-05-251-1/+4
| | | | | | | | | | | | | | switch early init to init_early and introduce soc map_io with this Patch we will not do any more early device setup during the map io tks to Russell to point the new call back Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Andrew Victor <linux@maxim.org.za>
* AT91: SAM9G45 - add a separate clock entry for every single TC blockFabian Godehardt2010-09-091-3/+12
| | | | | | | | | | | Without this patch you will not be able to register the first block because of the second association call on at91_add_device_tc(). Signed-off-by: Fabian Godehardt <fg@emlix.com> [nicolas.ferre@atmel.com: change tcb1_clk to fake child clock of tcb0_clk] Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* ARM: 6169/1: AT91: add new at91 chips in at91sam9g45 familyNicolas Ferre2010-06-161-0/+11
| | | | | | | | | | This is the basic support for at91sam9g46, at91sam9m10 and at91sam9m11. Those are just very basic cpu macros and clock definition. Signed-off-by: Patrice Vilchez <patrice.vilchez@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5572/1: at91: Support for at91sam9g45 series: core chip & board supportNicolas Ferre2009-06-271-0/+360
Here are the at91 specific files dedicated to the at91sam9g45 series. They mimic the traditional at91 way of managing chips & boards. The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES. In the future, the main board for this 9g45 series will be the AT91SAM9M10G45-EK (I choose this last name for the board file). Simple drivers are enabled in _devices and board- files. Newer peripheral support will be added in future patches. Incuded peripherals support (for now): - USART - SPI - Ethernet - NAND flash - LCD - gpio/joystick/buttons - leds and pwm Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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