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* ARM: imx: Use correct SRC base addressRobert Karszniewicz2020-12-011-1/+1
| | | | | | | | | | | Commit 4a4fb66119eb ("ARM: imx: Add missing of_node_put()") accidentally forgot to rename a variable, which caused the wrong address to be used and, in our case, the ULL getting falsely identified as ULZ. Fixes: 4a4fb66119eb ("ARM: imx: Add missing of_node_put()") Signed-off-by: Robert Karszniewicz <r.karszniewicz@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: imx: Remove unnecessary blank linesAnson Huang2020-03-111-1/+0
| | | | | | | Remove unnecessary blank lines for cleanup. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: imx: Add missing of_node_put()Anson Huang2020-02-181-2/+4
| | | | | | | | After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: imx: Drop imx_anatop_usb_chrg_detect_disable()Andrey Smirnov2019-10-281-19/+1
| | | | | | | | | | | | | | | | | | | | | | With commit b5bbe2235361 ("usb: phy: mxs: Disable external charger detect in mxs_phy_hw_init()") in tree all of the necessary charger setup is done by the USB PHY driver which covers all of the affected i.MX6 SoCs. NOTE: imx_anatop_usb_chrg_detect_disable() was also called for i.MX7D, but looking at its datasheet it appears to have a different USB PHY IP block, so executing i.MX6 charger disable configuration seems unnecessary. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peter Chen <peter.chen@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 159Thomas Gleixner2019-05-301-7/+1
| | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: imx: add i.mx6ulz msl supportAnson Huang2018-09-301-0/+20
| | | | | | | | | | | | | | | The i.MX 6ULZ processor is a high-performance, ultra cost-efficient consumer Linux processor featuring an advanced implementation of a single Arm® Cortex®-A7 core, which operates at speeds up to 900 MHz. This patch adds basic MSL support for i.MX6ULZ, the i.MX6ULZ has same soc_id as i.MX6ULL, and SRC_SBMR2 bit[6] is to differentiate i.MX6ULZ from i.MX6ULL, 1'b1 means i.MX6ULZ and 1'b0 means i.MX6ULL. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: imx: Improve the soc revision calculation flowBai Ping2018-02-121-37/+19
| | | | | | | | | | | | | | | | | | | | | On our i.MX6 SOC, the DIGPROG register is used for representing the SOC ID and silicon revision. The revision has two part: MAJOR and MINOR. each is represented in 8 bits in the register. bits [15:8]: reflect the MAJOR part of the revision; bits [7:0]: reflect the MINOR part of the revision; In our linux kernel, the soc revision is represented in 8 bits. MAJOR part and MINOR each occupy 4 bits. previous method does NOT take care about the MAJOR part in DIGPROG register. So reformat the revision read from the HW to be compatible with the revision format used in kernel. Signed-off-by: Bai Ping <ping.bai@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Tested-by: Christoph Fritz <chf.fritz@googlemail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: imx: Add msl code support for imx6qpBai Ping2016-02-141-1/+8
| | | | | | | | | | The i.MX6QP is a different SOC, but internally we treate it as i.MX6Q Rev_2.0 to maximum the code reusability. The chip silicon number we read from the ANADIG_DIGPROG is 0x630100. This patch add code to identify it as i.MX6QP Rev_1.0 when print out the silicon version. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: imx7d: correct chip version informationFrank Li2016-01-281-1/+8
| | | | | | | | | | | The commond 'cat /sys/devices/soc0/revision' can show correct soc version information. "unknow revision" message in imx_print_silicon_rev() will never work for digprog. Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: imx: add msl support for imx7dAnson Huang2015-06-031-1/+4
| | | | | | | | Add i.MX7D MSL support. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: add anatop settings for LPDDR2 when enter DSM modeAnson Huang2014-11-231-2/+32
| | | | | | | | | | | For LPDDR2 platform, no need to enable weak2P5 in DSM mode, it can be pulled down to save power(~0.65mW). And per design team's recommendation, we should disconnect VDDHIGH and SNVS in DSM mode on i.MX6SL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: i.MX6: add more chip revision supportJason Liu2014-09-161-0/+13
| | | | | | | | | | Add more revision support for the new i.MX6DQ tape-out (TO1.5). This TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3 and TO1.4 are never revealed. Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx: use imx_init_revision_from_anatop() on imx6slShawn Guo2013-10-211-1/+5
| | | | | | | Add imx6sl support into imx_init_revision_from_anatop(), so that it can be used to initialize cpu type and revision on imx6sl. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: add a common function to initialize revision from anatopShawn Guo2013-10-211-6/+21
| | | | | | | | | The patch creates a common function imx_init_revision_from_anatop() by merging imx6q_init_revision() and imx_anatop_get_digprog(), so that any SoC that encodes revision info in anatop can use it to initialize revision. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: Move anatop related from board file to anatop driverPeter Chen2013-08-221-1/+3
| | | | | | | Move anatop related (For USB) from board file to anatop driver Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: do not use regmap_read for ANADIG_DIGPROGShawn Guo2013-04-121-3/+12
| | | | | | | | | | | | | | | | | Function imx_anatop_get_digprog() that reads register ANADIG_DIGPROG is called to identify silicon version. Users might query silicon version earlier than regmap subsystem is ready. For example, imx6q clock driver query revision in mx6q_clocks_init(), where regmap is not initialized yet. Change imx_anatop_get_digprog() to map anatop block and read ANADIG_DIGPROG in the native way, so that the function can work at very early stage. While at it, let's move imx_print_silicon_rev() back to imx6q_timer_init() to have the message show up a little earlier. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: mach-imx: anatop: Include "common.h"Fabio Estevam2013-04-121-0/+1
| | | | | | | | | | | | | Fix the following sparse warnings: arch/arm/mach-imx/anatop.c:56:6: warning: symbol 'imx_anatop_pre_suspend' was not declared. Should it be static? arch/arm/mach-imx/anatop.c:62:6: warning: symbol 'imx_anatop_post_resume' was not declared. Should it be static? arch/arm/mach-imx/anatop.c:68:6: warning: symbol 'imx_anatop_usb_chrg_detect_disable' was not declared. Should it be static? arch/arm/mach-imx/anatop.c:78:5: warning: symbol 'imx_anatop_get_digprog' was not declared. Should it be static? arch/arm/mach-imx/anatop.c:86:13: warning: symbol 'imx_anatop_init' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: enable RBC to support anatop LPM modeAnson Huang2013-04-121-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | RBC is to control whether some ANATOP sub modules can enter lpm mode when SOC is into STOP mode, if RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP will have below behaviors: 1. Digital LDOs(CORE, SOC and PU) are bypassed; 2. Analog LDOs(1P1, 2P5, 3P0) are disabled; As the 2P5 is necessary for DRAM IO pre-drive in STOP mode, so we need to enable weak 2P5 in STOP mode when 2P5 LDO is disabled. For RBC settings, there are some rules as below due to hardware design: 1. All interrupts must be masked during operating RBC registers; 2. At least 2 CKIL(32K) cycles is needed after the RBC setting is changed. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: enable anatop suspend/resumeAnson Huang2013-04-121-0/+74
Anatop module have sereval configurations for user to reduce the power consumption in suspend, provide suspend/resume interface for further use and enable fet_odrive to reduce CORE LDO leakage during suspend. As we have a common anatop file, remove all the operations of anatop module in other files, use anatop interfaces to do that. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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