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* ARM: NOMMU: Introduce dma operations for noMMUVladimir Murzin2017-06-301-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R/M classes of cpus can have memory covered by MPU which in turn might configure RAM as Normal i.e. bufferable and cacheable. It breaks dma_alloc_coherent() and friends, since data can stuck in caches now or be buffered. This patch factors out DMA support for NOMMU configuration into separate entity which provides dedicated dma_ops. We have to handle there several cases: - configurations with MMU/MPU setup - configurations without MMU/MPU setup - special case for M-class, since caches and MPU there are optional In general we rely on default DMA area for coherent allocations or/and per-device memory reserves suitable for coherent DMA, so if such regions are set coherent allocations go from there. In case MMU/MPU was not setup we fallback to normal page allocator for DMA memory allocation. In case we run M-class cpus, for configuration without cache support (like Cortex-M3/M4) dma operations are forced to be coherent and wired with dma-noop (such decision is made based on cacheid global variable); however, if caches are detected there and no DMA coherent region is given (either default or per-device), dma is disallowed even MPU is not set - it is because M-class implement system memory map which defines part of address space as Normal memory. Reported-by: Alexandre Torgue <alexandre.torgue@st.com> Reported-by: Andras Szemzo <sza@esh.hu> Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Tested-by: Andras Szemzo <sza@esh.hu> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Russell King <rmk+kernel@armlinux.org.uk> [hch: removed the dma_supported() implementation that isn't required anymore] Signed-off-by: Christoph Hellwig <hch@lst.de>
* ARM: 8640/1: Add support for CONFIG_DEBUG_VIRTUALFlorian Fainelli2017-02-281-0/+1
| | | | | | | | | | | | | | x86 has an option: CONFIG_DEBUG_VIRTUAL to do additional checks on virt_to_phys calls. The goal is to catch users who are calling virt_to_phys on non-linear addresses immediately. This includes caller using __virt_to_phys() on image addresses instead of __pa_symbol(). This is a generally useful debug feature to spot bad code (particulary in drivers). Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Laura Abbott <labbott@redhat.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 8611/1: l2x0: add PMU supportMark Rutland2016-09-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | The L2C-220 (AKA L220) and L2C-310 (AKA PL310) cache controllers feature a Performance Monitoring Unit (PMU), which can be useful for tuning and/or debugging. This hardware is always present and the relevant registers are accessible to non-secure accesses. Thus, no special firmware interface is necessary. This patch adds support for the PMU, plugging into the usual perf infrastructure. The overflow interrupt is not always available (e.g. on RealView PBX A9 it is not wired up at all), and the hardware counters saturate, so the driver does not make use of this. Instead, the driver periodically polls and reset counters as required to avoid losing events due to saturation. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Pawel Moll <pawel.moll@arm.com> Tested-by: Kim Phillips <kim.phillips@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 8607/1: V7M: Wire up caches for V7M processors with cache support.Jonathan Austin2016-09-061-0/+2
| | | | | | | | | | | | | | | | This patch does the plumbing required to invoke the V7M cache code added in earlier patches in this series, although there is no users for that yet. In order to honour the I/D cache disable config options, this patch changes the mechanism by which the CCR is set on boot, to be more like V7A/R. Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Tested-by: Andras Szemzo <sza@esh.hu> Tested-by: Joachim Eastwood <manabian@gmail.com> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: uniphier: add outer cache supportMasahiro Yamada2015-10-271-0/+1
| | | | | | | | | | This commit adds support for UniPhier outer cache controller. All the UniPhier SoCs are equipped with the L2 cache, while the L3 cache is currently only integrated on PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
*-. Merge branches 'arnd-fixes', 'clk', 'misc', 'v7' and 'fixes' into for-nextRussell King2015-06-121-0/+1
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| | * ARM: re-implement physical address space switchingRussell King2015-06-011-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-implement the physical address space switching to be architecturally compliant. This involves flushing the caches, disabling the MMU, and only then updating the page tables. Once that is complete, the system can be brought back up again. Since we disable the MMU, we need to do the update in assembly code. Luckily, the entries which need updating are fairly trivial, and are all setup by the early assembly code. We can merely adjust each entry by the delta required. Not only does this fix the code to be architecturally compliant, but it fixes a couple of bugs too: 1. The original code would only ever update the first L2 entry covering a fraction of the kernel; the remainder were left untouched. 2. The L2 entries covering the DTB blob were likewise untouched. This solution fixes up all entries. Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* / ARM: 8381/1: fix ARMv4+Feroceon multiplatform buildArnd Bergmann2015-05-281-0/+2
|/ | | | | | | | | | The feroceon copypage implementation cannot be built when targetting an ARMv4 CPU, so we need to pass the march=armv5te flag manually to gcc when building this file. This is obviously safe since that code will not be executed on ARMv4. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 8238/1: mm: Refine set_memory_* functionsJungseung Lee2014-12-031-1/+1
| | | | | | | | | | | | set_memory_* functions have same implementation except memory attribute. This patch makes to use common function for these, and pull out the functions into arch/arm/mm/pageattr.c like arm64 did. It will reduce code size and enhance the readability. Signed-off-by: Jungseung Lee <js07.lee@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: provide common PL310 early resume codeRussell King2014-05-301-1/+1
| | | | | | | | | Provide a common assembly implementation for PL310 resume code. Certain platforms need to re-initialise the L2C cache early as it may preserve data across a S2RAM cycle, and therefore must be enabled along with the L1 cache and MMU. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: outer cache: add WARN_ON() to outer_disable()Russell King2014-05-301-0/+1
| | | | | | | Add WARN_ON() conditions to outer_disable() to ensure that its requirements aren't violated. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: add support to dump the kernel page tablesRussell King2013-12-111-0/+1
| | | | | | | | This patch allows the kernel page tables to be dumped via a debugfs file, allowing kernel developers to check the layout of the kernel page tables and the verify the various permissions and type settings. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'for-rmk/hugepages' of ↵Russell King2013-06-181-0/+1
|\ | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/stevecapper/linux into devel-stable These changes bring both HugeTLB support and Transparent HugePage (THP) support to ARM. Only long descriptors (LPAE) are supported in this series. The code has been tested on an Arndale board (Exynos 5250).
| * ARM: mm: HugeTLB support for LPAE systems.Catalin Marinas2013-06-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for hugetlbfs based on the x86 implementation. It allows mapping of 2MB sections (see Documentation/vm/hugetlbpage.txt for usage). The 64K pages configuration is not supported (section size is 512MB in this case). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> [steve.capper@linaro.org: symbolic constants replace numbers in places. Split up into multiple files, to simplify future non-LPAE support, removed huge_pmd_share code, as this is very rarely executed, Added PROT_NONE support]. Signed-off-by: Steve Capper <steve.capper@linaro.org> Reviewed-by: Will Deacon <will.deacon@arm.com>
* | Merge branch 'for-next' of git://git.pengutronix.de/git/ukl/linux into ↵Russell King2013-05-221-0/+2
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | devel-stable Pull ARM-v7M support from Uwe Kleine-König: "All but the last patch were in next since next-20130418 without issues. The last patch fixes a problem in combination with 8164f7a (ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register) which triggers a WARN_ON without an implemented read_cpuid_ext. The branch merges fine into v3.10-rc1 and I'd be happy if you pulled it for 3.11-rc1. The only missing piece to be able to run a Cortex-M3 is the irqchip driver that will go in via Thomas Gleixner and platform specific stuff."
| * ARM: ARMv7-M: Allow the building of new kernel portUwe Kleine-König2013-04-171-0/+2
| | | | | | | | | | | | | | | | | | | | This patch modifies the required Kconfig and Makefile files to allow the building of kernel for Cortex-M3. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Jonathan Austin <jonathan.austin@arm.com> Tested-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
* | ARM: cache: remove ARMv3 support codeWill Deacon2013-03-261-1/+0
|/ | | | | | | | | | | | | This is only used by 740t, which is a v4 core and (by my reading of the datasheet for the CPU) ignores CRm for the cp15 cache flush operation, making the v4 cache implementation in cache-v4.S sufficient for this CPU. Tested with 740T core-tile on Integrator/AP baseboard. Acked-by: Hyok S. Choi <hyok.choi@samsung.com> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM: 7644/1: vmregion: remove vmregion code entirelyJoonsoo Kim2013-02-161-1/+1
| | | | | | | | | | Now, there is no user for vmregion. So remove it. Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Joonsoo Kim <iamjoonsoo.kim@lge.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Remove support for ARMv3 ARM610 and ARM710 CPUsRussell King2012-05-051-4/+0
| | | | | | | | | | | | This patch removes support for ARMv3 CPUs, which haven't worked properly for quite some time (see the FIXME comment in arch/arm/mm/fault.c). The only V3 parts left is the cache model for ARMv3, which is needed for some odd reason by ARM740T CPUs, and being able to build with -march=armv3, which is required for the RiscPC platform due to its bus structure. Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: v6k: introduce CPU_V6K optionRussell King2011-02-021-0/+1
| | | | | | | | | | | | | | | | Introduce a CPU_V6K configuration option for platforms to select if they have a V6K CPU core. This allows us to identify whether we need to support ARMv6 CPUs without the V6K SMP extensions at build time. Currently CPU_V6K is just an alias for CPU_V6, and all places which reference CPU_V6 are replaced by (CPU_V6 || CPU_V6K). Select CPU_V6K from platforms which are known to be V6K-only. Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: pgtable: collect up identity mapping functionsRussell King2010-12-221-2/+2
| | | | | | | | | We have two places where we create identity mappings - one when we bring secondary CPUs online, and one where we setup some mappings for soft- reboot. Combine these two into a single implementation. Also collect the identity mapping deletion function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Remove DISCONTIGMEM supportRussell King2010-07-161-1/+0
| | | | | | | Everything should now be using sparsemem rather than discontigmem, so remove the code supporting discontigmem from ARM. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Ensure ARMv6/7 mm files are built using appropriate assembler optionsRussell King2010-01-121-0/+12
| | | | | | | | A kernel with both ARMv6 and ARMv7 selected results in build errors. Fix this by specifying the proper architectures for these assembly files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'devel-stable' into develRussell King2009-12-051-1/+1
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| * ARM: Add Tauros2 L2 cache controller supportLennert Buytenhek2009-11-271-1/+1
| | | | | | | | | | | | | | | | | | Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* | ARM: dma-mapping: split out vmregion code from dma coherent mapping codeRussell King2009-11-241-1/+1
|/ | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
* ARM: 5727/1: Pass IFSR register to do_PrefetchAbort()Kirill A. Shutemov2009-10-021-0/+4
| | | | | | | | | | | | | | | | | Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It needed for proper prefetch abort handling. Now we have three prefetch abort model: * legacy - for CPUs before ARMv6. They doesn't provide neither IFSR nor IFAR. We simulate IFSR with section translation fault status for them to generalize code; * ARMv6 - provides IFSR, but not IFAR; * ARMv7 - provides both IFSR and IFAR. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'for-rmk' of git://gitorious.org/linux-gemini/mainline into develRussell King2009-03-261-0/+4
|\ | | | | | | | | | | | | Conflicts: arch/arm/mm/Kconfig Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: Add support for FA526 v2Paulius Zaleckas2009-03-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for Faraday FA526 core. This core is used at least by: Cortina Systems Gemini and Centroid family Cavium Networks ECONA family Grain Media GM8120 Pixelplus ImageARM Prolific PL-1029 Faraday IP evaluation boards v2: - move TLB_BTB to separate patch - update copyrights Signed-off-by: Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
* | Merge branch 'highmem' into develRussell King2009-03-241-0/+1
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| * | [ARM] kmap supportNicolas Pitre2009-03-151-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kmap virtual area borrows a 2MB range at the top of the 16MB area below PAGE_OFFSET currently reserved for kernel modules and/or the XIP kernel. This 2MB corresponds to the range covered by 2 consecutive second-level page tables, or a single pmd entry as seen by the Linux page table abstraction. Because XIP kernels are unlikely to be seen on systems needing highmem support, there shouldn't be any shortage of VM space for modules (14 MB for modules is still way more than twice the typical usage). Because the virtual mapping of highmem pages can go away at any moment after kunmap() is called on them, we need to bypass the delayed cache flushing provided by flush_dcache_page() in that case. The atomic kmap versions are based on fixmaps, and __cpuc_flush_dcache_page() is used directly in that case. Signed-off-by: Nicolas Pitre <nico@marvell.com>
* / [ARM] pxa: add base support for Marvell's PXA168 processor lineEric Miao2009-03-231-0/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | """The Marvell® PXA168 processor is the first in a family of application processors targeted at mass market opportunities in computing and consumer devices. It balances high computing and multimedia performance with low power consumption to support extended battery life, and includes a wealth of integrated peripherals to reduce overall BOM cost .... """ See http://www.marvell.com/featured/pxa168.jsp for more information. 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core, there are many enhancements like instructions for flushing the whole D-cache, and so on 2. Clock reuses Russell's common clkdev, and added the basic support for UART1/2. 3. Devices are a bit different from the 'mach-pxa' way, the platform devices are now dynamically allocated only when necessary (i.e. when pxa_register_device() is called). Description for each device are stored in an array of 'struct pxa_device_desc'. Now that: a. this array of device description is marked with __initdata and can be freed up system is fully up b. which means board code has to add all needed devices early in his initializing function c. platform specific data can now be marked as __initdata since they are allocated and copied by platform_device_add_data() 4. only the basic UART1/2/3 are added, more devices will come later. Signed-off-by: Jason Chagas <chagas@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
* [ARM] dma: rename consistent.c to dma-mapping.cRussell King2008-09-251-1/+1
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'pxa' into develRussell King2008-07-131-0/+2
|\ | | | | | | | | | | | | Conflicts: arch/arm/configs/em_x270_defconfig arch/arm/configs/xm_x270_defconfig
| * [ARM] pxa: add support for L2 outer cache on XScale3Eric Miao2008-07-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial patch from Lothar, and Lennert make it into a cleaner one, modified and tested on PXA320 by Eric Miao. This patch moves the L2 cache operations out of proc-xsc3.S into dedicated outer cache support code. CACHE_XSC3L2 can be deselected so no L2 cache specific code will be linked in, and that L2 enable bit will not be set, this applies to the following cases: a. _only_ PXA300/PXA310 support included and no L2 cache wanted b. PXA320 support included, but want L2 be disabled So the enabling of L2 depends on two things: - CACHE_XSC3L2 is selected - and L2 cache is present Where the latter is only a safeguard (previous testing shows it works OK even when this bit is turned on). IXP series of processors with XScale3 cannot disable L2 cache for the moment since they depend on the L2 cache for its coherent memory, so IXP may always select CACHE_XSC3L2. Other L2 relevant bits are always turned on (i.e. the original code enclosed by #if L2_CACHE_ENABLED .. #endif), as they showed no side effects. Specifically, these bits are: - OC bits in TTBASE register (table walk outer cache attributes) - LLR Outer Cache Attributes (OC) in Auxiliary Control Register Signed-off-by: Lothar WaÃ<9f>mann <LW@KARO-electronics.de> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] Feroceon: L2 cache supportLennert Buytenhek2008-06-221-0/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the unified Feroceon L2 cache controller as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo families of ARM SoCs. Note that: - Page table walks are outer uncacheable on Kirkwood and Discovery Duo, since the ARMv5 spec provides no way to indicate outer cacheability of page table walks (specifying it in TTBR[4:3] is an ARMv6+ feature). This requires adding L2 cache clean instructions to proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to tlbflush.h ({flush,clean}_pmd_entry()). The latter case is handled by defining a new TLB type (TLB_FEROCEON) which is almost identical to the v4wbi one but provides a TLB_L2CLEAN_FR flag. - The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2 range by MVA' and 'invalidate L2 range by MVA') operations, and this patch uses those range operations for all Linux outer cache operations, as they are faster than the regular per-line operations. L2 range operations are not interruptible on this hardware, which avoids potential livelock issues, but can be bad for interrupt latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which allows you to select the maximum range size to operate on at once. (Valid range is between one cache line and one 4KiB page, and must be a multiple of the line size.) Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Feroceon: Feroceon-specific WA-cache compatible {copy,clear}_user_page()Lennert Buytenhek2008-04-281-0/+1
| | | | | | | | | | | | | | | This patch implements a set of Feroceon-specific {copy,clear}_user_page() routines that perform more optimally than the generic implementations. This also deals with write-allocate caches (Feroceon can run L1 D in WA mode) which otherwise prevents Linux from booting. [nico: optimized the code even further] Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Sylver Bruneau <sylver.bruneau@googlemail.com> Tested-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* [ARM] Marvell Feroceon CPU core supportAssaf Hoffman2008-01-261-0/+1
| | | | | | | | | | | | | | | | The Feroceon is a family of independent ARMv5TE compliant CPU core implementations, supporting a variable depth pipeline and out-of-order execution. The Feroceon is configurable with VFP support, and the later models in the series are superscalar with up to two instructions per clock cycle. This patch adds the initial low-level cache/TLB handling for this core. Signed-off-by: Assaf Hoffman <hoffman@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Reviewed-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4394/1: ARMv7: Add the TLB range operationsCatalin Marinas2007-05-301-0/+1
| | | | | | | | | We are currently using the ARMv6 operations but need to duplicate some of the code because of the introduction of the new CPU barrier instructions in ARMv7. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] armv7: add Makefile and Kconfig entriesCatalin Marinas2007-05-091-0/+3
| | | | | | | | This patch adds the necessary lines to the Makefile and Kconfig files for enabling the compilation of the ARMv7 CPU support. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4135/1: Add support for the L210/L220 cache controllersCatalin Marinas2007-02-111-0/+2
| | | | | | | | | This patch adds the support for the L210/L220 (outer) cache controller. The cache range operations are done by index/way since L2 cache controller only accepts physical addresses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.Hyok S. Choi2006-09-281-0/+1
| | | | | | | | | | There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a dummy abort handler which returns zero for the base restored Data Abort model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up for the base updated Data Abort model cores. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: add ARM946E-S core supportHyok S. Choi2006-09-271-0/+1
| | | | | | | | | | | This patch adds ARM946E-S core support which has typically 8KB I&D cache. It has a MPU and supports ARMv5TE instruction set. Because the ARM946E-S core can be synthesizable with various cache size, CONFIG_CPU_DCACHE_SIZE is defined for vendor specific configurations. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: add ARM940T core supportHyok S. Choi2006-09-271-0/+1
| | | | | | | | This patch adds ARM940T core support which has 4KB D-cache, 4KB I-cache and a MPU. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: add ARM9TDMI core supportHyok S. Choi2006-09-271-0/+1
| | | | | | | | This patch adds ARM9TDMI core support which has no cache and no CP15 register(no memory control unit). Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: add ARM740T core supportHyok S. Choi2006-09-271-0/+1
| | | | | | | This patch adds ARM740T core support which has a MPU and 4KB or 8KB cache. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: add ARM7TDMI core supportHyok S. Choi2006-09-271-0/+1
| | | | | | | | This patch adds ARM7TDMI core support which has no cache and no CP15 register(no memory control unit). Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Rename mm-armv.c to pgd.cRussell King2006-09-271-1/+1
| | | | | | | mm-armv.c now only contains the pgd allocation/freeing code, so rename it to have a more sensible filename. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Split ARM MM initialisation for !mmuRussell King2006-09-271-1/+1
| | | | | | | Move the MMU specific code from init.c into mmu.c, and add nommu fixups to nommu.c Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Move mmu.c out of the wayRussell King2006-09-201-1/+1
| | | | | | | Rename mmu.c to context.c - it's the ARMv6 ASID context handling code rather than generic "mmu" handling code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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