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| | | * | | ARM: l2c: only write the auxiliary control register if requiredRussell King2014-05-301-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid unnecessary writes to the auxiliary control register if the register already contains the required value. This allows us to avoid invoking the platforms secure monitor code unnecessarily. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: write auxctrl register before unlockingRussell King2014-05-301-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should write the auxillary control register before unlocking: the write may be necessary to enable non-secure access to the lock registers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: provide enable methodRussell King2014-05-301-18/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Providing an enable method gives L2 cache controllers a chance to do special handling at enable time. This allows us to remove a hack in l2x0_unlock() for Marvell Aurora L2 caches. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: group implementation specific code togetherRussell King2014-05-301-251/+251
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Back in the mists of time, someone decided that it would be a good idea to group like functions together - so all the save functions in one place, all the resume functions in another, all the OF parsing functions some place else. This makes it difficult to get an overview on what a particular implementation is doing - grouping an implementations specific functions together makes more sense, because you can see what it's doing without the clutter of other implementations. Organise it according to implementation. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: move l2c save function to __l2c_init()Russell King2014-05-301-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no reason this functionality should be specific to DT, so move it into the common initialisation function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: pass iomem address into data->save functionRussell King2014-05-301-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pass the iomem address into this function so we don't have to keep accessing it from a global. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: clean up OF initialisation a bitRussell King2014-05-301-26/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than having a boolean and other tricks to disable some bits of l2x0_init(), split this function into two parts: a common part shared between OF and non-OF, and the non-OF part. The common part can take a block of function pointers, and the cache ID (to cope with Aurora's DT specified ID.) Eliminate the redundant setting of l2x0_base in the OF case, moving it to the non-OF init function. This allows us to localise the OF-specific initialisation handling from the non-OF handling. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: add and use L2C revision constantsRussell King2014-05-301-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The revision namespace is specific to the L2 cache part, so don't name these with generic identifiers, use a part specific identifier. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: rename cache_wait_way()Russell King2014-05-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cache_wait_way() is actually used to wait for a particular mask to report clear; it's not really got much to do with cache ways at all. Indeed, it gets used to wait for the C bit to clear on older caches. Rename this with a more generic function name which better reflects its purpose: l2c_wait_mask(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: provide generic helper for way-based operationsRussell King2014-05-301-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a generic helper function for way based operations. These are always background operations, and thus have to be waited for before a new operation is commenced. This helper extracts that requirement from several locations in the code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: split out cache unlock codeRussell King2014-05-301-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the cache unlock code out of l2x0_unlock(). We want to be able to re-use this functionality later. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: provide generic function for calling set_debug methodRussell King2014-05-301-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a generic function which always calls the set_debug method. This will be used later in the series as some work-arounds require that the debug register be written. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: rename OF specific things, making l2x0_of_data available to allRussell King2014-05-301-32/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename a few things to help distinguish their function(s): l2x0_of_data -> l2c_init_data setup -> of_parse add of_ prefix to OF specific data Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: tidy up l2x0_of_data declarationsRussell King2014-05-301-16/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove NULL initialisers, make these all __initconst structures, and order their members in the same order as the structure declaration. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: add helper for L2 cache controller DT IDsRussell King2014-05-301-13/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make it easier to declare L2 cache controller DT IDs by using a macro. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: outer cache: add WARN_ON() to outer_disable()Russell King2014-05-302-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add WARN_ON() conditions to outer_disable() to ensure that its requirements aren't violated. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: l2c: remove outer_inv_all() methodRussell King2014-05-222-6/+0
| | | | |/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No one ever calls this function anywhere in the kernel, so let's completely remove it from the outer cache API and turn it into an internal-only thing. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: ensure C page table setup code follows assembly code (part II)Russell King2014-06-021-8/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This does the same as the previous commit, but for the S bit, which also needs to match the initial value which the assembly code used for the same reasons. Again, we add a check for SMP to ensure that the page tables are correctly setup for SMP. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: ensure C page table setup code follows assembly codeRussell King2014-06-021-16/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a long standing bug where, for ARMv6+, we don't fully ensure that the C code sets the same cache policy as the assembly code. This was introduced partially by commit 11179d8ca28d ([ARM] 4497/1: Only allow safe cache configurations on ARMv6 and later) and also by adding SMP support. This patch sets the default cache policy based on the flags used by the assembly code, and then ensures that when a cache policy command line argument is used, we verify that on ARMv6, it matches the initial setup. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: remove global cr_no_alignmentRussell King2014-06-022-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cr_no_alignment is really only used by the alignment code. Since we no longer change the setting of cr_alignment after boot, we can localise this to alignment.c Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: remove CPU_CP15 conditional from alignment.cRussell King2014-06-021-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | alignment.c will not be built unless CPU_CP15 is set: config CPU_CP15 bool config CPU_CP15_MMU bool select CPU_CP15 config ALIGNMENT_TRAP bool depends on CPU_CP15_MMU So there's no point having conditionals on CPU_CP15 within this code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: remove unused adjust_cr() functionRussell King2014-06-021-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | adjust_cr() is not used anymore, so let's get rid of it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: move "noalign" command line option to alignment.cRussell King2014-06-022-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keep all bits of alignment handling together. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: provide common method to clear bits in CPU control registerRussell King2014-06-024-9/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several places open-code this manipulation, let's consolidate this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: use get_cr() rather than cr_alignmentRussell King2014-05-221-1/+1
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | Rather than reading the cr_alignment variable, use get_cr() to read directly from the hardware instead. We have two places where this occurs, neither of them are performance critical. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | hugetlb: restrict hugepage_migration_support() to x86_64Naoya Horiguchi2014-06-041-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently hugepage migration is available for all archs which support pmd-level hugepage, but testing is done only for x86_64 and there're bugs for other archs. So to avoid breaking such archs, this patch limits the availability strictly to x86_64 until developers of other archs get interested in enabling this feature. Simply disabling hugepage migration on non-x86_64 archs is not enough to fix the reported problem where sys_move_pages() hits the BUG_ON() in follow_page(FOLL_GET), so let's fix this by checking if hugepage migration is supported in vma_migratable(). Signed-off-by: Naoya Horiguchi <n-horiguchi@ah.jp.nec.com> Reported-by: Michael Ellerman <mpe@ellerman.id.au> Tested-by: Michael Ellerman <mpe@ellerman.id.au> Acked-by: Hugh Dickins <hughd@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Tony Luck <tony.luck@intel.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Miller <davem@davemloft.net> Cc: <stable@vger.kernel.org> [3.12+] Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | | Merge tag 'devicetree-for-3.16' of ↵Linus Torvalds2014-06-041-1/+0
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next Pull DeviceTree updates from Rob Herring: - Another round of clean-up of FDT related code in architecture code. This removes knowledge of internal FDT details from most architectures except powerpc. - Conversion of kernel's custom FDT parsing code to use libfdt. - DT based initialization for generic serial earlycon. The introduction of generic serial earlycon support went in through the tty tree. - Improve the platform device naming for DT probed devices to ensure unique naming and use parent names instead of a global index. - Fix a race condition in of_update_property. - Unify the various linker section OF match tables and fix several function prototype errors. - Update platform_get_irq_byname to work in deferred probe cases. - 2 binding doc updates * tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (58 commits) of: handle NULL node in next_child iterators of/irq: provide more wrappers for !CONFIG_OF devicetree: bindings: Document micrel vendor prefix dt: bindings: dwc2: fix required value for the phy-names property of_pci_irq: kill useless variable in of_irq_parse_pci() of/irq: do irq resolution in platform_get_irq_byname() of: Add a testcase for of_find_node_by_path() of: Make of_find_node_by_path() handle /aliases of: Create unlocked version of for_each_child_of_node() lib: add glibc style strchrnul() variant of: Handle memory@0 node on PPC32 only pci/of: Remove dead code of: fix race between search and remove in of_update_property() of: Use NULL for pointers of: Stop naming platform_device using dcr address of: Ensure unique names without sacrificing determinism tty/serial: pl011: add DT based earlycon support of/fdt: add FDT serial scanning for earlycon of/fdt: add FDT address translation support serial: earlycon: add DT support ...
| * | | | Merge branch 'dt-bus-name' into for-nextRob Herring2014-05-132-5/+5
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| * | | | of/fdt: move memreserve and dtb memory reservations into coreRob Herring2014-04-301-1/+0
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the /memreserve/ processing and dtb memory reservations into early_init_fdt_scan_reserved_mem. This converts arm, arm64, and powerpc as they are the only users of early_init_fdt_scan_reserved_mem. memblock_reserve is safe to call on the same region twice, so the reservation check for the dtb in powerpc 32-bit reservations is safe to remove. Signed-off-by: Rob Herring <robh@kernel.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Tested-by: Grant Likely <grant.likely@linaro.org> Tested-by: Stephen Chivers <schivers@csc.com>
* | | | Merge branch 'for-v3.16' of ↵Linus Torvalds2014-06-031-8/+9
|\ \ \ \ | |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mszyprowski/linux-dma-mapping into next Pull CMA and DMA-mapping fixes from Marek Szyprowski: "A few fixes for dma-mapping and CMA subsystems" * 'for-v3.16' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping: CMA: correct unlock target drivers/base/dma-contiguous.c: erratum of dev_get_cma_area arm: dma-mapping: add checking cma area initialized arm: dma-iommu: Clean up redundant variable cma: Remove potential deadlock situation
| * | | arm: dma-mapping: add checking cma area initializedGioh Kim2014-05-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CMA is turned on and CMA size is set to zero, kernel should behave as if CMA was not enabled at compile time. Every dma allocation should check existence of cma area before requesting memory. Signed-off-by: Gioh Kim <gioh.kim@lge.com> Signed-off-by: Joonsoo Kim <iamjoonsoo.kim@lge.com> Acked-by: Michal Nazarewicz <mina86@mina86.com> [mszyprow: removed redundant empty line from the patch] Signed-off-by: <m.szyprowski@samsung.com>
| * | | arm: dma-iommu: Clean up redundant variableRitesh Harjani2014-05-201-5/+6
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | mapping->size can be derived from mapping->bits << PAGE_SHIFT which makes mapping->size as redundant. Clean this up. Signed-off-by: Ritesh Harjani <ritesh.harjani@gmail.com> Reported-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
* / | ARM: 8048/1: fix v7-M setup stack locationRabin Vincent2014-05-251-3/+5
|/ / | | | | | | | | | | | | | | | | | | | | __v7m_setup_stack currently sits in the .proc.info.init section, and thus creates a bogus proc info entry (which by the way matches any unknown CPU IDs, due to the entry's mask being 0). Move it out of there. Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'fixes_for_v3.15' of ↵Linus Torvalds2014-04-241-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mszyprowski/linux-dma-mapping Pull dma-mapping fix from Marek Szyprowski: "A small fix for dma-mapping subsystem for ARM" * 'fixes_for_v3.15' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping: arm: dma-mapping: Fix mapping size value
| * | arm: dma-mapping: Fix mapping size valueRitesh Harjani2014-04-231-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 68efd7d2fb("arm: dma-mapping: remove order parameter from arm_iommu_create_mapping()") is causing kernel panic because it wrongly sets the value of mapping->size: Unable to handle kernel NULL pointer dereference at virtual address 000000a0 pgd = e7a84000 [000000a0] *pgd=00000000 ... PC is at bitmap_clear+0x48/0xd0 LR is at __iommu_remove_mapping+0x130/0x164 Fix it by correcting mapping->size value. Signed-off-by: Ritesh Harjani <ritesh.harjani@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
* / ARM: keep arch/arm/Kconfig and arch/arm/mm/Kconfig select entries sortedRussell King2014-04-231-4/+4
|/ | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds2014-04-111-15/+32
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull second set of ARM changes from Russell King: "This is the remainder of the ARM changes for this merge window. Included in this request are: - fixes for kprobes for big-endian support - fix tracing in soft_restart - avoid phys address overflow in kdump code - fix reporting of read-only pmd bits in kernel page table dump - remove unnecessary (and possibly buggy) call to outer_flush_all() - fix a three sparse warnings (missing header file for function prototypes) - fix pj4 crashing single zImage (thanks to arm-soc merging changes which enables this with knowledge that the corresponding fix had not even been submitted for my tree before the merge window opened) - vfp macro cleanups - dump register state on undefined instruction userspace faults when debugging" * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: Dump the registers on undefined instruction userspace faults ARM: 8018/1: Add {inc,dec}_preempt_count asm macros ARM: 8017/1: Move asm macro get_thread_info to asm/assembler.h ARM: 8016/1: Check cpu id in pj4_cp0_init. ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it has some differences with V7 ARM: add missing system_misc.h include to process.c ARM: 8009/1: dcscb.c: remove call to outer_flush_all() ARM: 8014/1: mm: fix reporting of read-only PMD bits ARM: 8012/1: kdump: Avoid overflow when converting pfn to physaddr ARM: 8010/1: avoid tracers in soft_restart ARM: kprobes-test: Workaround GAS .align bug ARM: kprobes-test: use <asm/opcodes.h> for Thumb instruction building ARM: kprobes-test: use <asm/opcodes.h> for ARM instruction building ARM: kprobes-test: use <asm/opcodes.h> for instruction accesses ARM: probes: fix instruction fetch order with <asm/opcodes.h>
| *-. Merge branches 'fixes' and 'misc' into for-nextRussell King2014-04-111-15/+32
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| | * | ARM: 8014/1: mm: fix reporting of read-only PMD bitsKees Cook2014-04-071-15/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On non-LPAE ARMv6+, read-only PMD bits are defined with the combination "PMD_SECT_APX | PMD_SECT_AP_WRITE". Adjusted the bit masks to correctly report this. Signed-off-by: Kees Cook <keescook@chromium.org> Tested-by: Laura Abbott <lauraa@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | Merge tag 'soc-3.15' of ↵Linus Torvalds2014-04-053-30/+46
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC specific changes from Arnd Bergmann: "Lots of changes specific to one of the SoC families. Some that stick out are: - mach-qcom gains new features, most importantly SMP support for the newer chips (Stephen Boyd, Rohit Vaswani) - mvebu gains support for three new SoCs: Armada 375, 380 and 385 (Thomas Petazzoni and Free-electrons team) - SMP support for Rockchips (Heiko Stübner) - Lots of i.MX changes (Shawn Guo) - Added support for BCM5301x SoC (Hauke Mehrtens) - Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn and Sebastian Hesselbarth doing the final part of a long journey) - Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd Bergmann)" * tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (126 commits) ARM: sunxi: Select HAVE_ARM_ARCH_TIMER ARM: cache-tauros2: remove ARMv6 code ARM: mvebu: don't select CONFIG_NEON ARM: davinci: fix DT booting with default defconfig ARM: configs: bcm_defconfig: enable bcm590xx regulator support ARM: davinci: remove tnetv107x support MAINTAINERS: Update ARM STi maintainers ARM: restrict BCM_KONA_UART to ARCH_BCM_MOBILE ARM: bcm21664: Add board support. ARM: sunxi: Add the new watchog compatibles to the reboot code ARM: enable ARM_HAS_SG_CHAIN for multiplatform ARM: davinci: remove da8xx_omapl_defconfig ARM: davinci: da8xx: fix multiple watchdog device registration ARM: davinci: add da8xx specific configs to davinci_all_defconfig ARM: davinci: enable da8xx build concurrently with older devices ARM: BCM5301X: workaround suppress fault ARM: BCM5301X: add early debugging support ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU ARM: mach-bcm: Remove GENERIC_TIME ARM: shmobile: APMU: Fix warnings due to improper printk formats ...
| * | | | ARM: cache-tauros2: remove ARMv6 codeArnd Bergmann2014-03-271-28/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building a kernel with support for both ARMv6 and ARMv7 but no MMU, the call from tauros2_internal_init to adjust_cr causes a link error. While that could probably be resolved, we don't actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU implementations support both ARMv6 and ARMv7 and we already assume that we are using them only in ARMv7 mode. Removing the ARMv6 code path reduces the code size and avoids the linker error. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
| * | | | Merge tag 'mvebu-soc-3.15-2' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann2014-03-172-2/+45
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/soc Merge "mvebu soc changes for v3.15 (incremental pull #2)" from Jason Cooper: - mvebu - Add Armada 375, 380 and 385 SoCs - kirkwood - move kirkwood DT support to mach-mvebu - add mostly DT support for HP T5325 thin client * tag 'mvebu-soc-3.15-2' of git://git.infradead.org/linux-mvebu: ARM: kirkwood: Add HP T5325 thin client ARM: kirkwood: select dtbs based on SoC ARM: kirkwood: Remove redundant kexec code ARM: mvebu: Armada 375/38x depend on MULTI_V7 ARM: mvebu: Simplify headers and make local ARM: mvebu: Enable mvebu-soc-id on Kirkwood ARM: mvebu: Let kirkwood use the system controller for restart ARM: mvebu: Move kirkwood DT boards into mach-mvebu ARM: MM Enable building Feroceon L2 cache controller with ARCH_MVEBU ARM: Fix default CPU selection for ARCH_MULTI_V5 ARM: MM: Add DT binding for Feroceon L2 cache ARM: orion: Move cache-feroceon-l2.h out of plat-orion ARM: mvebu: Add ARCH_MULTI_V7 to SoCs ARM: kirkwood: ioremap memory control register ARM: kirkwood: ioremap the cpu_config register before using it. ARM: kirkwood: Separate board-dt from common and pcie code. ARM: kirkwood: Drop printing the SoC type and revision ARM: kirkwood: Convert mv88f6281gtw_ge switch setup to DT ARM: kirkwood: Give pm.c its own header file. ARM: mvebu: Rename the ARCH_MVEBU menu option Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | | | ARM: MM Enable building Feroceon L2 cache controller with ARCH_MVEBUAndrew Lunn2014-02-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kirkwood, which uses the Feroceon L2 cache controller will soon be moving into mach-mvebu. Allow the cache controller to be built in this situation. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * | | | ARM: MM: Add DT binding for Feroceon L2 cacheAndrew Lunn2014-02-221-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * | | | ARM: orion: Move cache-feroceon-l2.h out of plat-orionAndrew Lunn2014-02-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the gradual move to DT, kirkwood has become a lot less dependent on plat-orion. cache-feroceon-l2.h is the last dependency. Move it out so we can drop plat-orion when building DT only kirkwood boards. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | | | | | Merge tag 'fixes-non-critical-3.15' of ↵Linus Torvalds2014-04-051-1/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC non-critical bug fixes from Arnd Bergmann: "Lots of isolated bug fixes that were not found to be important enough to be submitted before the merge window or backported into stable kernels. The vast majority of these came out of Arnd's randconfig testing and just prevents running into build-time bugs in configurations that we do not care about in practice" * tag 'fixes-non-critical-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (75 commits) ARM: at91: fix a typo ARM: moxart: fix CPU selection ARM: tegra: fix board DT pinmux setup ARM: nspire: Fix compiler warning IXP4xx: Fix DMA masks. Revert "ARM: ixp4xx: Make dma_set_coherent_mask common, correct implementation" IXP4xx: Fix Goramo Multilink GPIO conversion. Revert "ARM: ixp4xx: fix gpio rework" ARM: tegra: make debug_ll code build for ARMv6 ARM: sunxi: fix build for THUMB2_KERNEL ARM: exynos: add missing include of linux/module.h ARM: exynos: fix l2x0 saved regs handling ARM: samsung: select CRC32 for SAMSUNG_PM_CHECK ARM: samsung: select ATAGS where necessary ARM: samsung: fix SAMSUNG_PM_DEBUG Kconfig logic ARM: samsung: allow serial driver to be disabled ARM: s5pv210: enable IDE support in MACH_TORBRECK ARM: s5p64x0: fix building with only one soc type ARM: s3c64xx: select power domains only when used ARM: s3c64xx: MACH_SMDK6400 needs HSMMC1 ...
| * \ \ \ \ \ Merge branch 'randconfig-fixes' into next/fixes-non-criticalArnd Bergmann2014-03-221-1/+1
| |\ \ \ \ \ \ | | |/ / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the first batch of a much longer series of bug fixes found during randconfig testing. This part are all the simple patches that are applicable for the arm-soc tree, while most other fixes will likely go through other maintainers. * randconfig-fixes: (50 commits) ARM: tegra: make debug_ll code build for ARMv6 ARM: sunxi: fix build for THUMB2_KERNEL ARM: exynos: add missing include of linux/module.h ARM: exynos: fix l2x0 saved regs handling ARM: samsung: select CRC32 for SAMSUNG_PM_CHECK ARM: samsung: select ATAGS where necessary ARM: samsung: fix SAMSUNG_PM_DEBUG Kconfig logic ARM: samsung: allow serial driver to be disabled ARM: s5pv210: enable IDE support in MACH_TORBRECK ARM: s5p64x0: fix building with only one soc type ARM: s3c64xx: select power domains only when used ARM: s3c64xx: MACH_SMDK6400 needs HSMMC1 ARM: s3c24xx: osiris dvs needs tps65010 ARM: s3c24xx: fix gta02 build error ARM: s3c24xx: MINI2440 needs I2C for EEPROM_AT24 ARM: integrator: only select pl01x if TTY is enabled ARM: realview: fix sparsemem build ARM: footbridge: make screen_info setup conditional ARM: footbridge: fix build with PCI disabled ARM: footbridge: don't build floppy code for addin mode ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | | | | ARM: rpc: autoselect CPU_SA110Arnd Bergmann2014-03-211-1/+1
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARCH_RPC no longer supports other CPUs aside from StrongARM110, so we can make the option implicitly selected by the platform and no longer give the option of building a kernel without CPU support. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk>
* | | | | | Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds2014-04-057-26/+31
|\ \ \ \ \ \ | | |_|/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM changes from Russell King: - Perf updates from Will Deacon: - Support for Qualcomm Krait processors (run perf on your phone!) - Support for Cortex-A12 (run perf stat on your FPGA!) - Support for perf_sample_event_took, allowing us to automatically decrease the sample rate if we can't handle the PMU interrupts quickly enough (run perf record on your FPGA!). - Basic uprobes support from David Long: This patch series adds basic uprobes support to ARM. It is based on patches developed earlier by Rabin Vincent. That approach of adding hooks into the kprobes instruction parsing code was not well received. This approach separates the ARM instruction parsing code in kprobes out into a separate set of functions which can be used by both kprobes and uprobes. Both kprobes and uprobes then provide their own semantic action tables to process the results of the parsing. - ARMv7M (microcontroller) updates from Uwe Kleine-König - OMAP DMA updates (recently added Vinod's Ack even though they've been sitting in linux-next for a few months) to reduce the reliance of omap-dma on the code in arch/arm. - SA11x0 changes from Dmitry Eremin-Solenikov and Alexander Shiyan - Support for Cortex-A12 CPU - Align support for ARMv6 with ARMv7 so they can cooperate better in a single zImage. - Addition of first AT_HWCAP2 feature bits for ARMv8 crypto support. - Removal of IRQ_DISABLED from various ARM files - Improved efficiency of virt_to_page() for single zImage - Patch from Ulf Hansson to permit runtime PM callbacks to be available for AMBA devices for suspend/resume as well. - Finally kill asm/system.h on ARM. * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (89 commits) dmaengine: omap-dma: more consolidation of CCR register setup dmaengine: omap-dma: move IRQ handling to omap-dma dmaengine: omap-dma: move register read/writes into omap-dma.c ARM: omap: dma: get rid of 'p' allocation and clean up ARM: omap: move dma channel allocation into plat-omap code ARM: omap: dma: get rid of errata global ARM: omap: clean up DMA register accesses ARM: omap: remove almost-const variables ARM: omap: remove references to disable_irq_lch dmaengine: omap-dma: cleanup errata 3.3 handling dmaengine: omap-dma: provide register read/write functions dmaengine: omap-dma: use cached CCR value when enabling DMA dmaengine: omap-dma: move barrier to omap_dma_start_desc() dmaengine: omap-dma: move clnk_ctrl setting to preparation functions dmaengine: omap-dma: improve efficiency loading C.SA/C.EI/C.FI registers dmaengine: omap-dma: consolidate clearing channel status register dmaengine: omap-dma: move CCR buffering disable errata out of the fast path dmaengine: omap-dma: provide register definitions dmaengine: omap-dma: consolidate setup of CCR dmaengine: omap-dma: consolidate setup of CSDP ...
| * | | | | Merge branch 'devel-stable' into for-nextRussell King2014-04-041-1/+1
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