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* Merge branch 'ixp4xx' into develRussell King2007-05-061-0/+28
|\ | | | | | | | | | | Conflicts: include/asm-arm/arch-ixp4xx/io.h
| * [ARM] 4311/1: ixp4xx: add KIXRP435 platformRuslan V. Sushko2007-04-211-0/+28
| | | | | | | | | | | | | | | | | | | | Add Intel KIXRP435 Reference Platform based on IXP43x processor. Fixed after review : access to cp15 removed in identification functions, used access to global processor_id instead Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Signed-off-by: Ruslan Sushko <rsushko@ru.mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm 10: allow memory type to be specified with ioremapRussell King2007-05-052-17/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | __ioremap() took a set of page table flags (specifically the cacheable and bufferable bits) to control the mapping type. However, with the advent of ARMv6, this is far too limited. Replace the page table flags with a memory type index, so that the desired attributes can be selected from the mem_type table. Finally, to prevent silent miscompilation due to the differing arguments, rename the __ioremap() and __ioremap_pfn() functions. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm 9: add additional device memory typesRussell King2007-05-051-22/+28
| | | | | | | | | | | | | | Add cached device type for ioremap_cached(). Group all device memory types together, and ensure that they all have a "MT_DEVICE" prefix. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm 8: define mem_types table L1 bit 4 to be for ARMv6Russell King2007-05-051-24/+20
| | | | | | | | | | | | | | Change the memory types table to define the L1 descriptor bit 4 to be in terms of the ARMv6 definition - execute never. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm 6: allow mem_types table to specify extended pte attributesRussell King2007-04-213-2/+5
| | | | | | | | | | | | | | | | Add prot_pte_ext to the mem_types table to allow the extended pte attributes to be passed to set_pte_ext(), thereby permitting us to specify memory type information for the hardware PTE entries. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm 5: Use mem_types table in ioremapRussell King2007-04-213-46/+42
| | | | | | | | | | | | | | We really want to be using the memory type table in ioremap, so we only have to do the CPU type fixups in one place. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm 4: make create_mapping() more conventionalRussell King2007-04-211-59/+55
| | | | | | | | | | | | | | | | | | Rather than our three separate loops to setup mappings (by page mappings up to a section boundary, then section mappings, and the remainder by page mappings) convert this to a more conventional Linux style of a loop over each page table level. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm 3: separate out supersection mappings, avoid for <4GBRussell King2007-04-212-70/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Catalin Marinas at ARM Ltd says: > The CPU architects in ARM intended supersections only as a way to map > addresses >= 4GB. Supersections are not mandated by the architecture > and there is no easy way to detect their hardware support at run-time > (other than checking for a specific core). From the analysis done in > ARM, there wasn't a clear performance gain by using supersections > rather than sections (no significant improvement in the TLB misses). Therefore, we should avoid using supersections unless there's a real need (iow, we're mapping addresses >= 4GB). This means that we can simplify create_mapping() a bit since we will only use supersection mappings for addresses >= 4GB, which means that the physical, virtual and length must be multiples of the supersection mapping size. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm 2: clean up create_mapping()Russell King2007-04-211-17/+13
| | | | | | | | | | | | | | | | There's now no need to carry around each protection separately. Instead, pass around the pointer to the entry in the mem_types array which we're interested in. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm 1: Combine mem_type domain into prot_* at init timeRussell King2007-04-211-4/+12
|/ | | | | | | | | | | Rather than combining the domain for a particular memory type with the protection information each time we want to use it, do so when we fix up the mem_type array at initialisation time. Rename struct mem_types to be mem_type - each structure is one memory type description, not several. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Remove needless linux/ptrace.h includesRussell King2007-04-213-3/+0
| | | | | | | | | Lots of places in arch/arm were needlessly including linux/ptrace.h, resumably because we used to pass a struct pt_regs to interrupt handlers. Now that we don't, all these ptrace.h includes are redundant. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Add ability to dump exception stacks to kernel backtracesRussell King2007-04-211-2/+2
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivialLinus Torvalds2007-02-191-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial: (25 commits) Documentation/kernel-docs.txt update. arch/cris: typo in KERN_INFO Storage class should be before const qualifier kernel/printk.c: comment fix update I/O sched Kconfig help texts - CFQ is now default, not AS. Remove duplicate listing of Cris arch from README kbuild: more doc. cleanups doc: make doc. for maxcpus= more visible drivers/net/eexpress.c: remove duplicate comment add a help text for BLK_DEV_GENERIC correct a dead URL in the IP_MULTICAST help text fix the BAYCOM_SER_HDX help text fix SCSI_SCAN_ASYNC help text trivial documentation patch for platform.txt Fix typos concerning hierarchy Fix comment typo "spin_lock_irqrestore". Fix misspellings of "agressive". drivers/scsi/a100u2w.c: trivial typo patch Correct trivial typo in log2.h. Remove useless FIND_FIRST_BIT() macro from cardbus.c. ...
| * kbuild: Replace remaining "depends" with "depends on"Robert P. J. Day2007-02-171-1/+1
| | | | | | | | | | | | | | | | Replace the very few remaining "depends" Kconfig directives with "depends on". Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* | Merge NetSilicon NS93xx treeRussell King2007-02-181-2/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | Fixed conflicts: arch/arm/Makefile arch/arm/mm/Kconfig Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] 4210/1: base for new machine type "NetSilicon NS9360"Uwe Kleine-König2007-02-171-2/+2
| |/ | | | | | | | | Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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*-----. \ Merge AT91, EP93xx, General devel, PXA, S3C, V6+ and Xscale treesRussell King2007-02-178-95/+228
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| | | | * [ARM] 4123/1: xsc3: general cleanupLennert Buytenhek2007-02-081-76/+75
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up proc-xsc3: - Correct a number of typos. - Fix up indentation in a number of places. - Change references to the various caches to be more clear about whether we're talking about the L1 D, the L1 I or the unified L2 cache. - Rename "drain write buffer" to "data write barrier", the official name used in the Manzano manual. - Change the xsc3 cpu name from "XScale-Core3" to "XScale-V3 based processor". Also, since a previously merged patch implements proper support for using a MAC or iWMMXt coprocessor on xsc3 platforms, we no longer need to enable access to CP0 on boot. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * Merge Realview GIC codeRussell King2007-02-151-3/+5
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| | | | * [ARM] 4109/2: Add support for the RealView/EB MPCore revC platformCatalin Marinas2007-02-151-3/+5
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel originally supported revB only. This patch enables revC by default and adds a config option for building the kernel for the revB platform. Since the SCU base address was hard-coded in the proc-v6.S file (and only valid for RealView/EB revB), this patch also adds a more generic support for defining the SCU information. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 4135/1: Add support for the L210/L220 cache controllersCatalin Marinas2007-02-113-0/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the support for the L210/L220 (outer) cache controller. The cache range operations are done by index/way since L2 cache controller only accepts physical addresses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Always mark ARMv6 PTWs outer cacheableRussell King2007-02-081-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other platforms other than SMP may have an outer cache. For these, we also need to mark the page table walks outer cacheable. Since marking the walks always outer cacheable apparantly has no side effects, we might as well always mark them so. However, we continue to only mark PTWs shared if we have SMP enabled. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 4153/1: fix consistent_sync() off-by-one BUG checkLennert Buytenhek2007-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In consistent_sync(), start + size can end up pointing one byte beyond the end of the direct RAM mapping. We shouldn't BUG() when this happens. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Convert DMA cache handling to take const void * argsRussell King2007-02-081-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA cache handling functions take virtual addresses, but in the form of unsigned long arguments. This leads to a little confusion about what exactly they take. So, convert them to take const void * instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 4134/1: Add generic support for outer cachesCatalin Marinas2007-02-082-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The outer cache can be L2 as on RealView/EB MPCore platform or even L3 or further on ARMv7 cores. This patch adds the generic support for flushing the outer cache in the DMA operations. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 4129/1: Add barriers after the TLB operationsCatalin Marinas2007-02-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The architecture specification states that TLB operations are guaranteed to be complete only after the execution of a DSB (Data Synchronisation Barrier, former Data Write Barrier or Drain Write Buffer). The branch target cache invalidation is also needed. The ISB (Instruction Synchronisation Barrier, formerly Prefetch Flush) is needed unless there will be a return from exception before the corresponding mapping is used (i.e. user mappings). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 4128/1: Architecture compliant TTBR changing sequenceCatalin Marinas2007-02-081-2/+10
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On newer architectures (ARMv6, ARMv7), the depth of the prefetch and branch prediction is implementation defined and there is a small risk of wrong ASID tagging when changing TTBR0 before setting the new context id. The recommended solution is to set a reserved ASID during TTBR changing. This patch reserves ASID 0. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * / [ARM] 4145/2: AT91: Add support for AT91SAM9263 processorAndrew Victor2007-02-081-2/+2
| |/ | | | | | | | | | | | | | | | | | | Add support for the Atmel AT91SAM9263 processor. It is similar to the AT91SAM9260 but with more integrated peripherals, 5 GPIO banks, etc. Original patch from Nicolas Ferre. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 4191/1: Remove redundant __flush_dcache_page() function prototypeGeorge G. Davis2007-02-161-2/+0
| | | | | | | | | | | | | | | | | | | | Commit 1c9d3df5e88ad7db23f5b22f4341c39722a904a4 added function prototype __flush_dcache_page() in include/asm-arm/cacheflush.h. So we can remove the prototype for same in arch/arm/mm/fault-armv.c since it is now redundant to have it there. Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 4158/1: Fix user page protection macrosImre_Deak2007-02-111-0/+3
|/ | | | | | | | | | The PAGE_* user page protection macros don't take into account the configured memory policy and other architecture specific bits like the global/ASID and shared mapping bits. Instead of constants let these depend on a variable fixed up at init just like PAGE_KERNEL. Signed-off-by: Imre Deak <imre.deak@solidboot.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4112/1: Only ioremap to supersections if DOMAIN_IO is zeroCatalin Marinas2007-01-251-1/+2
| | | | | | | | | Supersections do not have a field for the domain and it is always 0. This patch prevents the creation of supersections during ioremap when DOMAIN_IO is not zero (i.e. !defined(CONFIG_IO_36)). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4100/1: iop3xx: fix cpu mask for iop333Dan Williams2007-01-241-1/+1
| | | | | | | | cosmetic fix so iop333 is not reported as ixp46x iop333 cpuid = 0x69054210 Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix show_mem() for discontigmemRussell King2007-01-241-4/+7
| | | | | | | | show_mem() was assuming incorrectly that the mem_map for any node started at PFN 0. This is obviously wrong; fix it to take account of node_start_pfn. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Resolve fuse and direct-IO failures due to missing cache flushesRussell King2007-01-081-0/+39
| | | | | | | | | | | | | | | fuse does not work on ARM due to cache incoherency issues - fuse wants to use get_user_pages() to copy data from the current process into kernel space. However, since this accesses userspace via the kernel mapping, the kernel mapping can be out of date wrt data written to userspace. This can lead to unpredictable behaviour (in the case of fuse) or data corruption for direct-IO. This resolves debian bug #402876 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4078/1: Fix ARM copypage cache coherency problemsRichard Purdie2006-12-303-0/+16
| | | | | | | | | | | | | If PG_dcache_dirty is set for a page, we need to flush the source page before performing any copypage operation using a different virtual address. This fixes the copypage implementations for XScale, StrongARM and ARMv6. This patch fixes segmentation faults seen in the dynamic linker under the usage patterns in glibc 2.4/2.5. Signed-off-by: Richard Purdie <rpurdie@rpsys.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4061/1: xsc3: change of maintainerLennert Buytenhek2006-12-191-1/+1
| | | | | | | Deepak Saxena has agreed to hand xsc3 maintainership over to me. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix warnings from asm/system.hRussell King2006-12-181-0/+20
| | | | | | | Move adjust_cr() into arch/arm/mm/mmu.c, and move irqflags.h to a more appropriate place in the header file. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix BUG()s in ioremap() codeRussell King2006-12-171-0/+2
| | | | | | | | We need to ensure that the area size is page aligned so that remap_area_pte() doesn't increment the address past the end of the desired area. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Clean up ioremap codeRussell King2006-12-131-58/+40
| | | | | | | Since we're keeping the ioremap code, we might as well keep it as close to the standard kernel as possible. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Unuse another Linux PTE bitRussell King2006-12-1325-75/+71
| | | | | | | | | | L_PTE_ASID is not really required to be stored in every PTE, since we can identify it via the address passed to set_pte_at(). So, create set_pte_ext() which takes the address of the PTE to set, the Linux PTE value, and the additional CPU PTE bits which aren't encoded in the Linux PTE value. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Formalise the ARMv6 processor name stringRussell King2006-12-081-1/+1
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Handle HWCAP_VFP in VFP support codeRussell King2006-12-082-7/+2
| | | | | | | | | | | | Don't set HWCAP_VFP in the processor support file; not only does it depend on the processor features, but it also depends on the support code being present. Therefore, only set it if the support code detects that we have a VFP coprocessor attached. Also, move the VFP handling of the coprocessor access register into the VFP support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2006-12-0724-39/+43
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (76 commits) [ARM] 4002/1: S3C24XX: leave parent IRQs unmasked [ARM] 4001/1: S3C24XX: shorten reboot time [ARM] 3983/2: remove unused argument to __bug() [ARM] 4000/1: Osiris: add third serial port in [ARM] 3999/1: RX3715: suspend to RAM support [ARM] 3998/1: VR1000: LED platform devices [ARM] 3995/1: iop13xx: add iop13xx support [ARM] 3968/1: iop13xx: add iop13xx_defconfig [ARM] Update mach-types [ARM] Allow gcc to optimise arm_add_memory a little more [ARM] 3991/1: i.MX/MX1 high resolution time source [ARM] 3990/1: i.MX/MX1 more precise PLL decode [ARM] 3986/1: H1940: suspend to RAM support [ARM] 3985/1: ixp4xx clocksource cleanup [ARM] 3984/1: ixp4xx/nslu2: Fix disk LED numbering (take 2) [ARM] 3994/1: ixp23xx: fix handling of pci master aborts [ARM] 3981/1: sched_clock for PXA2xx [ARM] 3980/1: extend the ARM Versatile sched_clock implementation from 32 to 63 bit [ARM] 3979/1: extend the SA11x0 sched_clock implementation from 32 to 63 bit period [ARM] 3978/1: macro to provide a 63-bit value from a 32-bit hardware counter ...
| *-. [ARM] Merge individual ARM sub-treesRussell King2006-12-0724-39/+43
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge: Atmel AT91RM9200 and AT91SAM9260 changes General ARM developments Disconfiguous memory cleanups 64-bit/32-bit division and sched_clock extension patches EP93xx support changes IOP support changes Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3995/1: iop13xx: add iop13xx supportDan Williams2006-12-071-1/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * [ARM] 3999/1: RX3715: suspend to RAM supportBen Dooks2006-12-071-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RX3715 is similar to the H1940 in the way that suspend to RAM works, so we can use most of the extant support for the H1940 with only a few modifictions Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * [ARM] 3986/1: H1940: suspend to RAM supportBen Dooks2006-12-071-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to suspend and resume, using the H1940's bootloader Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * [ARM] 3881/4: xscale: clean up cp0/cp1 handlingLennert Buytenhek2006-12-031-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XScale cores either have a DSP coprocessor (which contains a single 40 bit accumulator register), or an iWMMXt coprocessor (which contains eight 64 bit registers.) Because of the small amount of state in the DSP coprocessor, access to the DSP coprocessor (CP0) is always enabled, and DSP context switching is done unconditionally on every task switch. Access to the iWMMXt coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is first issued, and iWMMXt context switching is done lazily. CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will have iWMMXt support', but boards are supposed to select this config symbol by hand, and at least one pxa27x board doesn't get this right, so on that board, proc-xscale.S will incorrectly assume that we have a DSP coprocessor, enable CP0 on boot, and we will then only save the first iWMMXt register (wR0) on context switches, which is Bad. This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on might have iWMMXt support, and we will enable iWMMXt context switching if it does.' This means that with this patch, running a CONFIG_IWMMXT=n kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt state over context switches, and running a CONFIG_IWMMXT=y kernel on a non-iWMMXt capable CPU will still do DSP context save/restore. These changes should make iWMMXt work on PXA3xx, and as a side effect, enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined), as well as setting and using HWCAP_IWMMXT properly. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * [ARM] 3967/1: xsc3: make branch predication configurable on xsc3Dan Williams2006-12-012-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove BTB_ENABLE from proc-xsc3.S On some early revisions of xsc3 enabling the branch target buffer can cause crashes, see erratum #42. Cc: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 00:30:29 +0000