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* arm64: dts: juno: enable some SMMUsRobin Murphy2017-05-191-4/+0
| | | | | | | | | | | | | | | | | | The IOMMU-backed DMA API support has now been in place for a while and proven stable, so there's no real need to keep most of Juno's SMMUs disabled. The USB, HDLCDs, and CoreSight ETR all just need to map RAM buffers for DMA - enabling their SMMUs obviates CPU bounce buffering for USB's streaming DMA to the upper memory bank, and lets the other two allocate their relatively large coherent buffers without pressuring CMA. Some more software work is still needed for the DMA-330 and PCIe before those can accommodate SMMU translation correctly in all cases, so we leave those alone for now. Tested-by: Liviu Dudau <Liviu.Dudau@arm.com> [only HDLCD] Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: add coresight CPU debug nodesSuzuki K Poulose2017-05-194-0/+126
| | | | | | | | | | | | | Add Coresight CPU debug nodes for Juno r0, r1 & r2. The CPU debug areas are mapped at the same address for all revisions, like the ETM, even though the CPUs have changed from r1 to r2. Cc: Leo Yan <leo.yan@linaro.org> Cc: Mathieu Poirier <mathieu.porier@linaro.org> Cc: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> [arranged nodes in ascending order with respect to register addresses] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: add information about L1 and L2 cachesSudeep Holla2017-04-193-0/+126
| | | | | | | | | | | | | | | | | | Commit a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache information probing") removed mechanism to extract cache information based on CCSIDR register as the architecture explicitly states no inference about the actual sizes of caches based on CCSIDR registers. Commit 9a802431c527 ("arm64: cacheinfo: add support to override cache levels via device tree") had already provided options to override cache information from the device tree. This patch adds the information about L1 and L2 caches on all variants of Juno platform. Cc: Will Deacon <will.deacon@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: fix few unit address format warningsSudeep Holla2017-04-192-7/+7
| | | | | | | | | | | | | | | This patch fixes the following set of warnings on juno. smb@08000000 unit name should not have leading 0s sysctl@020000 simple-bus unit address format error, expected "20000" apbregs@010000 simple-bus unit address format error, expected "10000" mmci@050000 simple-bus unit address format error, expected "50000" kmi@060000 simple-bus unit address format error, expected "60000" kmi@070000 simple-bus unit address format error, expected "70000" wdt@0f0000 simple-bus unit address format error, expected "f0000" Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: fix PCI bus dtc warningsRob Herring2017-03-311-1/+1
| | | | | | | | | dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* Merge tag 'juno-fixes-4.11' of ↵Arnd Bergmann2017-03-021-6/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/late Merge "ARMv8 Juno DT fix for v4.11" from Sudeep Holla: Just single patch to fix replicator in order to prevent overflows at the source and reduce the back pressure by splitting the trace output to TPIU and ETR. * tag 'juno-fixes-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: update definition for programmable replicator
| * arm64: dts: juno: update definition for programmable replicatorMike Leach2017-02-211-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Juno platforms have a programmable replicator splitting the trace output to TPIU and ETR. Currently this is not being programmed as it is being treated as a none-programmable replicator - which is the default operational mode for these devices. The TPIU in the system is enabled by default, and this combination is causing back-pressure in the trace system resulting in overflows at the source. Replaces the existing definition with one that defines the programmable replicator, using the "qcom,coresight-replicator1x" driver that provides the correct functionality for CoreSight programmable replicators. Reviewed-and-Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* | Merge tag 'juno-updates-4.11' of ↵Olof Johansson2017-01-187-26/+186
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64 ARMv8 Vexpress/Juno DT updates for v4.11 1. Addition of Coresight support on Juno R1 and R2 variants 2. Addition of STM(System Trace Macrocell) support on all Juno variants 3. Removed incorrect nesting of dtsi files 4. Removed untested USB hub only available on initial Juno R0 motherboard 5. Added ETR SMMU power domain and dma-ranges property * tag 'juno-updates-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: remove motherboard USB node arm64: dts: juno: add ETR SMMU power domain arm64: dts: juno: add dma-ranges property arm64: dts: juno: add missing CoreSight STM component arm64: dts: juno: add CoreSight support for Juno r1/r2 variants arm64: dts: juno: refactor CoreSight support on Juno r0 arm64: dts: juno: remove dtsi nesting inside tree structure Signed-off-by: Olof Johansson <olof@lixom.net>
| * arm64: dts: juno: remove motherboard USB nodeRobin Murphy2017-01-181-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first batch of Juno boards included a discrete USB controller chip as a contingency in case of issues with the USB 2.0 IP integrated into the SoC. As it turned out, the latter was fine, and to the best of my knowledge the motherboard USB was never even brought up and validated. Since this also isn't present on later boards, and uses a compatible string undocumented and unmatched by any driver in the kernel, let's just tidy it away for ever to avoid any confusion. Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: juno: add ETR SMMU power domainRobin Murphy2017-01-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not at all clear from the documentation, but straightforward to determine in practice, that the ETR SMMU is actually in the DEBUGSYS power domain. Add that to the DT so that anyone brave enough to enable said SMMU doesn't experience a system lockup on boot, especially a sneaky one which goes away as soon as you connect an external debugger to have a look at where it's stuck (thus powering up DEBUGSYS by other means and allowing it to make progress again before actually halting...) Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: juno: add dma-ranges propertyRobin Murphy2017-01-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | The interconnects around Juno have a 40-bit address width, and DMA masters have no restrictions beyond their own individual limitations. Describe this to ensure that DT-based DMA masks get set up correctly for all devices capable of 40-bit addressing. Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: juno: add missing CoreSight STM componentMike Leach2017-01-184-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the missing CoreSight STM component definition to the device tree of all the juno variants(r0,r1,r2) STM component is connected to different funnels depending on Juno platform variant. Reviewed-and-tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mike Leach <mike.leach@linaro.org> [sudeep.holla@arm.com: minor changelog update and reorganising the STM node back into juno-base.dtsi to avoid duplication] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: juno: add CoreSight support for Juno r1/r2 variantsMike Leach2017-01-183-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CoreSight support added for Juno is valid for only Juno r0. The Juno r1 and r2 variants have additional components and alternative connection routes between trace source and sinks. This patch builds on top of the existing r0 support and extends it to Juno r1/r2 variants. Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mike Leach <mike.leach@linaro.org> [sudeep.holla@arm.com: minor changelog update and major reorganisation of the common coresight components back into juno-base.dtsi to avoid duplication, also renamed funnel node names] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: juno: refactor CoreSight support on Juno r0Sudeep Holla2017-01-182-10/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently the Coresight components are supported only on Juno r0 variant. In preparation to add support to Juno r1/r2 variants, this patch refactors the existing coresight device nodes so that r1/r2 support can be added easily. It also cleans up some of the device node names which were previously named so as they were confused as the labels rather than the node names. Reviewed-and-tested-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: juno: remove dtsi nesting inside tree structureSudeep Holla2017-01-185-9/+9
| | | | | | | | | | | | | | | | | | | | | | Currently juno-clock.dtsi and juno-base.dtsi are nested badly inside the device tree structure. It's generally good practice to ensure that individual dtsi stand by themselves at the top of the file. This patch removes the nesting of the above mentioned dtsi files and makes them independent. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* | arm64: dts: vexpress: Support GICC_DIR operationsSudeep Holla2016-12-301-1/+1
|/ | | | | | | | | | | | | The GICv2 CPU interface registers span across 8K, not 4K as indicated in the DT. Only the GICC_DIR register is located after the initial 4K boundary, leaving a functional system but without support for separately EOI'ing and deactivating interrupts. After this change the system supports split priority drop and interrupt deactivation. This patch is based on similar one from Christoffer Dall: commit 368400e242dc ("ARM: dts: vexpress: Support GICC_DIR operations") Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* Merge tag 'armsoc-dt64' of ↵Linus Torvalds2016-12-154-0/+98
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources: - Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time: - Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...
| * arm64: dts: juno: add cpu capacity-dmips-mhz information to R2 boardsJuri Lelli2016-10-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds cpu capacity-dmips-mhz information to Juno R2 boards. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Jon Medhurst <tixy@linaro.org> Cc: Olof Johansson <olof@lixom.net> Cc: Robin Murphy <robin.murphy@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Juri Lelli <juri.lelli@arm.com> [sudeep.holla@arm.com: reformated subject and updated changelog] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: juno: add cpu capacity-dmips-mhz information to R1 boardsJuri Lelli2016-10-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds cpu capacity-dmips-mhz information to Juno R1 boards. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Jon Medhurst <tixy@linaro.org> Cc: Olof Johansson <olof@lixom.net> Cc: Robin Murphy <robin.murphy@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Juri Lelli <juri.lelli@arm.com> [sudeep.holla@arm.com: reformated subject and updated changelog] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: juno: add cpu capacity-dmips-mhz information to R0 boardsJuri Lelli2016-10-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds cpu capacity-dmips-mhz information to Juno R0 boards. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Jon Medhurst <tixy@linaro.org> Cc: Olof Johansson <olof@lixom.net> Cc: Robin Murphy <robin.murphy@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Juri Lelli <juri.lelli@arm.com> [sudeep.holla@arm.com: reformated subject and updated changelog] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: juno: Add SMMUs device nodesRobin Murphy2016-10-171-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Juno has separate MMU-401 instances in front of the DMA-330, both HDLCD controllers, the USB host controller, the PCIe root complex, and the CoreSight ETR. Since there is still work to do to make all the relevant subsystems interact nicely with the presence of an IOMMU, add the nodes to aid development and testing but leave them disabled by default to avoid nasty surprises. CC: Liviu Dudau <liviu.dudau@arm.com> CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> [sudeep.holla@arm.com: reformated subject] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* | arm64: dts: juno: fix cluster sleep state entry latency on all SoC versionsSudeep Holla2016-12-023-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core and the cluster sleep state entry latencies can't be same as cluster sleep involves more work compared to core level e.g. shared cache maintenance. Experiments have shown on an average about 100us more latency for the cluster sleep state compared to the core level sleep. This patch fixes the entry latency for the cluster sleep state. Fixes: 28e10a8f3a03 ("arm64: dts: juno: Add idle-states to device tree") Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: "Jon Medhurst (Tixy)" <tixy@linaro.org> Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | arm64: dts: juno: Correct PCI IO windowJeremy Linton2016-11-301-1/+1
|/ | | | | | | | | | The PCIe root complex on Juno translates the MMIO mapped at 0x5f800000 to the PIO address range starting at 0 (which is common because PIO addresses are generally < 64k). Correct the DT to reflect this. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: dts: juno: add thermal zones for scpi sensorsJavi Merino2016-06-213-0/+74
| | | | | | | | | | | | | | The juno dts have entries for the hwmon scpi, let's create thermal zones for the temperature sensors described in the Juno ARM Development Platform Implementation Details. Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Javi Merino <javi.merino@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: add SCPI power domains for device power managementSudeep Holla2016-06-211-0/+18
| | | | | | | | | This patch adds power domain information to coresight devices using SCPI power domains. Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: add coresight supportSudeep Holla2016-06-214-0/+369
| | | | | | | | | | | | | | | | | | | | | | | | | Most of the debug-related components on Juno are located in the coreSight subsystem while others are located in the Cortex-Axx clusters, the SCP subsystem, and in the main system. Each core in the two processor clusters contain an Embedded Trace Macrocell(ETM) which generates real-time trace information that trace tools can use and an ATB trace output that is sent to a funnel before going to the CoreSight subsystem. The trace output signals combine with two trace expansions using another funnel and fed into the Embedded Trace FIFO(ETF0). The output trace data stream of the funnel is then replicated before it is sent to either the: - Trace Port Interface Unit(TPIU), that sends it out using the trace port. - ETR that can write the trace data to memory located in the application memory space Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: Add external expansion bus to DTBrian Starkey2016-04-151-0/+10
| | | | | | | | | | | The Juno development platform has an external expansion bus which can be used for additional hardware (e.g. LogicTile Express daughterboards). Add this bus to the Juno base device-tree. Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"Masahiro Yamada2016-03-123-3/+3
| | | | | | | | | | | | | | | | The compatible string "simple-bus" is well defined in ePAPR, while I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or Documentation/devicetree/. DT is also used by other projects than Linux kernel. It is not a good idea to rely on such an unofficial binding. This commit - replaces "arm,amba-bus" with "simple-bus" - drops "arm,amba-bus" where it is used along with "simple-bus" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* Merge tag 'vexpress-for-v4.6/dt-updates-2' of ↵Olof Johansson2016-03-126-36/+44
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt Additional updates for ARM VExpress/Juno platforms 1. Add support for SBSA Generic Watchdog on foundation models 2. Fix node name unit-address presence/absence mismatch warnings in all the device trees * tag 'vexpress-for-v4.6/dt-updates-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno/vexpress: fix node name unit-address presence warnings arm64: dts: foundation-v8: add SBSA Generic Watchdog device node Signed-off-by: Olof Johansson <olof@lixom.net>
| * arm64: dts: juno/vexpress: fix node name unit-address presence warningsSudeep Holla2016-03-086-36/+36
| | | | | | | | | | | | | | | | | | | | | | | | Commit fa38a82096a1 ("scripts/dtc: Update to upstream version 53bf130b1cdd") added warnings on node name unit-address presence/absence mismatch in device trees. This patch fixes those warning on all the juno/vexpress platforms where unit-address is present in node name while the reg/ranges property is not present. It also adds unit-address to all smb bus node. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: foundation-v8: add SBSA Generic Watchdog device nodeFu Wei2016-03-081-0/+8
| | | | | | | | | | | | | | | | | | | | This can be a example of adding SBSA Generic Watchdog device node into some dts files for the Soc which contains SBSA Generic Watchdog. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Fu Wei <fu.wei@linaro.org> [edited subject and moved change to dtsi file] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* | Merge tag 'vexpress-for-v4.6/dt-updates' of ↵Olof Johansson2016-02-247-250/+515
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt Few updates for ARM VExpress/Juno platforms 1. GICv3 support on Foundation models 2. Support for Juno R2 board 3. Support for ARM HDLCD on all Juno platforms * tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: Add HDLCD support on Juno platforms Documentation: drm: Add DT bindings for ARM HDLCD arm64: dts: Add support for Juno r2 board arm64: dts: move juno pcie-controller to base file arm64: dts: add .dts for GICv3 Foundation model arm64: dts: split Foundation model dts to put the GIC separately arm64: dts: Foundation model: increase GICC region to allow EOImode=1 arm64: dts: prepare foundation-v8.dts to cope with GICv3 Signed-off-by: Olof Johansson <olof@lixom.net>
| * arm64: dts: Add HDLCD support on Juno platformsLiviu Dudau2016-02-101-4/+42
| | | | | | | | | | | | | | | | | | ARM's Juno platforms have two HDLCD controllers, each linked to an NXP TDA19988 HDMI transmitter that provides output encoding. Add them to the device tree. Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
| * arm64: dts: Add support for Juno r2 boardSudeep Holla2016-02-092-1/+184
| | | | | | | | | | | | | | | | | | Juno r2 is identical to Juno r1 with Cortex A57 cores replaced by Cortex A72 cores. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: move juno pcie-controller to base fileSudeep Holla2016-02-092-21/+26
| | | | | | | | | | | | | | | | | | | | | | | | The PCIe controller is found on all Juno SoC version. However it's not functional on R0 due to some hardware bug. In preparation to add Juno R2 support, this patch moves the pcie-controller defination to base DTS file. It's marked as disabled by default and is enabled for Juno R1 explicitly. Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: add .dts for GICv3 Foundation modelAndre Przywara2016-02-092-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | The ARMv8 Foundation model sports a command line parameter to use a GICv3 emulation instead of the default GICv2 interrupt controller. Add a new .dts file which reuses most of the definitions of the existing model while just adding the required properties for the GICv3 node. This allows the public Foundation model to run with a GICv3. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: split Foundation model dts to put the GIC separatelyAndre Przywara2016-02-092-221/+230
| | | | | | | | | | | | | | | | | | | | | | | | The ARMv8 Foundation model can be run with a GICv2 or a GICv3. To prepare for the GICv3 version of the .dts without code duplication, move most of the nodes of the existing DT (except the GIC) into an include file and just keep that include statement and the GIC node in the current foundation-v8.dts. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: Foundation model: increase GICC region to allow EOImode=1Andre Przywara2016-02-091-1/+1
| | | | | | | | | | | | | | | | | | | | The Foundation model GIC mapping is wrong, as the GICC region should be 8kB instead of 4kB (the model implements the GICv2 architecture). This defect prevents the driver from switching to EOImode==1. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| * arm64: dts: prepare foundation-v8.dts to cope with GICv3Andre Przywara2016-02-091-44/+44
| | | | | | | | | | | | | | | | | | | | To prepare the ARM foundation model to support GICv3, we adjust the #address-cells property of the current GICv2 node to be compatible with the two cells required for GICv3 later. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* | arm64: dts: Add missing DMA Abort interrupt to JunoRobin Murphy2016-02-011-0/+1
|/ | | | | | | | | | | | | The DMA-330 has an "irq_abort" interrupt line on which it signals faults separately from the "irq[n:0]" channel interrupts. On Juno, this is wired up to SPI 92; add it to the DT so that DMAC faults are correctly reported for the driver to reset the thing, rather than leaving it locked up and waiting to time out. CC: Liviu Dudau <liviu.dudau@arm.com> CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* arm64: dts: juno: Add idle-states to device treeJon Medhurst (Tixy)2015-12-222-0/+56
| | | | | | | | | | | This patch adds idle-states bindings data collected through a set of benchmarking experiments (latency and energy consumption) on Juno boards. Latencies data represents the worst case scenarios as required by the DT idle-states bindings. Signed-off-by: Jon Medhurst <tixy@linaro.org> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2015-11-106-1/+160
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As usual, this is the massive branch we have for each release. Lots of various updates and additions of hardware descriptions on existing hardware, as well as the usual additions of new boards and SoCs. This is also the first release where we've started mixing 64- and 32-bit DT updates in one branch. (Specific details on what's actually here and new is pretty easy to tell from the diffstat, so there's little point in duplicating listing it here)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits) ARM: dts: uniphier: add system-bus-controller nodes ARM64: juno: disable NOR flash node by default ARM: dts: uniphier: add outer cache controller nodes arm64: defconfig: Enable PCI generic host bridge by default arm64: Juno: Add support for the PCIe host bridge on Juno R1 Documentation: of: Document the bindings used by Juno R1 PCIe host bridge ARM: dts: uniphier: add I2C aliases for ProXstream2 boards dts/Makefile: Add build support for LS2080a QDS & RDB board DTS dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards dts/ls2080a: Update Simulator DTS to add support of various peripherals dts/ls2080a: Remove text about writing to Free Software Foundation dts/ls2080a: Update DTSI to add support of various peripherals doc: DTS: Update DWC3 binding to provide reference to generic bindings doc/bindings: Update GPIO devicetree binding documentation for LS2080A Documentation/dts: Move FSL board-specific bindings out of /powerpc Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards arm64: Rename FSL LS2085A SoC support code to LS2080A arm64: Use generic Layerscape SoC family naming ARM: dts: uniphier: add ProXstream2 Vodka board support ARM: dts: uniphier: add ProXstream2 Gentil board support ...
| * Merge branch 'next/arm64' into next/dtOlof Johansson2015-11-091-0/+20
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merging in the few patches I had kept separate from main next/dt, since others got merged here directly. * next/arm64: arm64: defconfig: Enable PCI generic host bridge by default arm64: Juno: Add support for the PCIe host bridge on Juno R1 Documentation: of: Document the bindings used by Juno R1 PCIe host bridge arm64: dts: mt8173: Add clocks for SCPSYS unit arm64: dts: mt8173: Add subsystem clock controller device nodes + Linux 4.3-rc5
| | * arm64: Juno: Add support for the PCIe host bridge on Juno R1Liviu Dudau2015-10-261-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Juno R1 board sports a functional PCIe host bridge that is compliant with the SBSA standard found [1] here. With the right firmware that initialises the XpressRICH3 controller one can use the generic Host Bridge driver to use the PCIe hardware. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0029a/
| * | ARM64: juno: disable NOR flash node by defaultLinus Walleij2015-10-311-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After discussing on the mailing list it turns out that accessing the flash memory from the kernel can disrupt CPU sleep states and CPU hotplugging, so let's disable this DT node by default. Setups that want to access the flash can modify this entry to enable the flash again. Quoting Sudeep Holla: "the firmware assumes the flash is always in read mode while Linux leaves NOR flash in "read id" mode after initialization." Reported-by: Sudeep Holla <sudeep.holla@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Leif Lindholm <leif.lindholm@arm.com> Cc: Ryan Harkin <ryan.harkin@linaro.org> Fixes: 5078f77e1443 "ARM64: juno: add NOR flash to device tree" Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | Merge tag 'juno-scpi-for-v4.4' of ↵Arnd Bergmann2015-10-153-0/+123
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt Merge "SCPI support on ARM64 Juno Development Platform" from Sudeep Holla: 1. SRAM, MHU mailbox and SCPI support 2. CPU topology using cpu-map 3. Clock support for all the cpus 4. Support for SoC sensors * tag 'juno-scpi-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: Add sensor node to Juno dt arm64: dts: add clock support for all the cpus arm64: dts: add CPU topology on Juno arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno
| | * | arm64: dts: Add sensor node to Juno dtPunit Agrawal2015-10-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SCP firmware on Juno provides access to SoC sensors via the SCPI. Add the sensor nodes to the device tree to enable this support. Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com>
| | * | arm64: dts: add clock support for all the cpusSudeep Holla2015-10-092-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the CPU clocks so that the CPU DVFS can be enabled. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
| | * | arm64: dts: add CPU topology on JunoSudeep Holla2015-10-092-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds CPU topology on Juno. It will be useful for ther other IP blocks depending on this topology. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
| | * | arm64: dts: add SRAM, MHU mailbox and SCPI support on JunoSudeep Holla2015-10-091-0/+54
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the MHU mailbox peripheral used on Juno by application processors to communicate with remote SCP handling most of the CPU/system power management. It also adds the SRAM reserving the shared memory and SCPI message protocol using that shared memory. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-19 08:07:02 +0000