summaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/socionext
Commit message (Collapse)AuthorAgeFilesLines
* arm64: dts: uniphier: make compatible of syscon nodes SoC-specificMasahiro Yamada2016-11-052-6/+6
| | | | | | | | | These hardware blocks are SoC-specific, so their compatible strings should be SoC-specific as well. This change has no impact on the actual behavior since it is controlled by the generic "simple-mfd", "syscon" compatible strings. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoCMasahiro Yamada2016-11-051-0/+84
| | | | | | | | | | | | | | Add a CPU clock to every CPU node and CPU OPP tables to use the generic cpufreq driver. All the CPUs in each cluster share the same OPP table. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
* arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoCMasahiro Yamada2016-11-051-0/+38
| | | | | | | | | | | | | Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
* arm64: dts: uniphier: increase register region size of sysctrl nodeMasahiro Yamada2016-11-052-2/+2
| | | | | | | | The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because the registers controlling CPU frequency are located at offset 0x8000. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* arm64: dts: uniphier: switch over to PSCI enable methodMasahiro Yamada2016-11-052-14/+18
| | | | | | | | | | | At the first system bring-up, I chose to use spin-table because ARM Trusted Firmware was not ready for this platform at that moment. Actually, these SoCs are equipped with EL3 and able to provide PSCI. Now I finished porting the ATF BL31 for the UniPhier platform, so it is ready to migrate to PSCI enable method. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* arm64: dts: uniphier: change MIO node to SD control nodeMasahiro Yamada2016-10-221-6/+6
| | | | | | | I made a mistake bacuse the Media I/O block is not implemented in this SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'dt/irq-fix' into next/dt64Arnd Bergmann2016-09-141-4/+4
|\ | | | | | | | | | | | | | | * dt/irq-fix: arm64: dts: Fix broken architected timer interrupt trigger This resolves a non-obvious conflict between a bugfix from v4.8 and a cleanup for the exynos7 platform.
| * arm64: dts: Fix broken architected timer interrupt triggerMarc Zyngier2016-09-141-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | arm64: dts: uniphier: add LD11 SoC/Board supportMasahiro Yamada2016-08-313-1/+441
| | | | | | | | | | | | This is a low-cost 64bit SoC from Socionext. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm64: dts: uniphier: add specific compatible to SoC-Glue nodeMasahiro Yamada2016-08-311-1/+2
| | | | | | | | | | | | This is a simple MFD, but add a specific compatible just in case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm64: dts: uniphier: use clock/reset controllersMasahiro Yamada2016-08-311-22/+58
| | | | | | | | | | | | | | | | The UniPhier reset controller driver has been merged. Enable it. Also, replace the fixed-rate clocks with the dedicated clock drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm64: dts: uniphier: add pinctrl property to System Bus nodeMasahiro Yamada2016-08-301-0/+2
| | | | | | | | | | | | This pinctrl is needed to get access to the UniPhier System Bus. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm64: dts: uniphier: match DT names to other projects and documentsMasahiro Yamada2016-08-303-10/+12
|/ | | | | | | | All UniPhier device trees have the common prefix "uniphier-", so "ph1-" is just making names longer. Recent documents and other projects are not using PH1- prefixes any more. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* arm64: dts: uniphier: add /memreserve/ for spin-table release addressMasahiro Yamada2016-06-141-0/+2
| | | | | | | | | As Documentation/arm64/booting.txt says, the cpu-release-addr location should be reserved. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* arm64: dts: uniphier: change cpu-release-addressMasahiro Yamada2016-06-141-4/+4
| | | | | | | | | | At first, 256 byte of the head of DRAM space was reserved for some reasons. However, as the progress of development, it turned out unnecessary, and it was never used in the end. Move the CPU release address to leave no space. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCsMasahiro Yamada2016-06-141-3/+7
| | | | | | | This node consists of various system-level configuration registers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* Merge tag 'armsoc-dt64' of ↵Linus Torvalds2016-05-183-0/+8
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Arnd Bergmann: "We continue ramping up platform support for 64-bit ARM machines, with 111 individual non-merge changesets touching 21 platforms. The LG1312 platform is completely new and is the first ARM platform by LG that we support in the mainline kernel. Two other SoCs got added that are updated versions of existing SoC families, so the port mainly consists of new dts files: - The Hisilicon Hip06/D03 is the latest server platform from Huawei/Hisilicon, and follows the Hip05/D02 platform. - Rockchip RK3399 follows the 32-bit RK3288 that is popular in low-end Chromebooks and the 64-bit RK3368 that is mainly found in chinese Android TV boxes. The 96Boards HiKey based on the Hisilicon Hi6220 (Kirin 620) gets a long-awaited overhaul with a lot of devices enabled in the DT, so it should be much more usable with a mainline kernel now. See also https://plus.google.com/111524780435806926688/posts/PeGb2VsNhJd A lot of work went into enabling new device drivers on existing machines, but we also have a couple of new commercially available machines: - Google Pixel C laptop based on Tegra210 - Hardkernel Odroid C2 Based on Amlogic Meson GXBB (S905) - Geekbuying GeekBox based on Rockchip RK3368 And finally, a couple of reference or development platforms that are not end-user platforms but are used for trying out the respective SoC platforms: - Amlogic Meson GXBB P200 and P201 development systems - NXP Layerscape 1043A QDS development board - Hisilicon Hip06 D03 server board, as mentioned above - LG1312 Reference Design - RK3399 Evaluation Board" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (104 commits) arm64: dts: marvell: add XOR node for Armada 3700 SoC dt-bindings: document rockchip rk3399-evb board arm64: dts: rockchip: add dts file for RK3399 evaluation board arm64: dts: rockchip: add core dtsi file for RK3399 SoCs dt-bindings: rockchip-dw-mshc: add description for rk3399 arm64: dts: marvell: Use a SoC-specific compatible for xHCI on Armada37xx arm64: dts: marvell: Rename armada-37xx USB node arm64: dts: marvell: Clean up armada-3720-db Documentation: arm64: Add Hisilicon Hip06 D03 dts binding arm64: dts: Add initial dts for Hisilicon Hip06 D03 board arm64: dts: hip05: Add nor flash support arm64: dts: hip05: fix its node without msi-cells arm64: dts: r8a7795: Don't disable referenced optional clocks arm64: dts: salvator-x: populate EXTALR arm64: dts: r8a7795: enable PCIe on Salvator-X arm64: dts: r8a7795: Add PCIe nodes arm64: tegra: Add IOMMU node to GM20B on Tegra210 arm64: tegra: Add reference clock to GM20B on Tegra210 dt-bindings: Add documentation for GM20B GPU dt-bindings: gk20a: Document iommus property ...
| * arm64: dts: uniphier: add reference clock node for PH1-LD20Masahiro Yamada2016-04-251-0/+6
| | | | | | | | | | | | | | Add a master clock node generated by a 25MHz crystal oscillator. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * arm64: dts: uniphier: use Daughter board on PH1-LD20 reference boardMasahiro Yamada2016-04-252-0/+2
| | | | | | | | | | | | | | | | Include the development base board, which is equipped with some devices such as EEPROM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | arm64: dts: uniphier: fix I2C nodes of PH1-LD20Masahiro Yamada2016-04-232-16/+5
|/ | | | | | | | | | | | | | | | | The I2C hardware blocks on this SoC are connected as follows: I2C0: external connection I2C1: external connection I2C2: internal connection I2C3: external connection I2C4: external connection I2C5: internal connection I2C6: no connection (not accessible) Delete pinctrl from Ch2, add pinctrl to Ch4, and remove the Ch6 node. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: uniphier: rework UniPhier System Bus nodesMasahiro Yamada2016-03-181-6/+13
| | | | | | | | | | | | | During the review process of the UniPhier System Bus driver (drivers/bus/uniphier.c), the current binding of the System Bus Controller turned out to be no good. In order to make the driver really usable, we have to switch over to the new binding defined by Documentation/devicetree/bindings/bus/uniphier-system-bus.txt. The old binding will be still supported for a while to keep the backward compatibility. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: uniphier: factor out ranges property of support cardMasahiro Yamada2016-03-181-8/+0
| | | | | | | | | This property is used in common by several boards. Move it to the common place (uniphier-support-card.dtsi). If necessary, each board can still override the property. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: dts: uniphier: rename PH1-LD10 to PH1-LD20Masahiro Yamada2016-03-183-8/+8
| | | | | | | | | Due to the company's awful projecting, this chip has been renamed to PH1-LD20. It has not been shipped yet, this change would have no impact on our customers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: dts: uniphier: add PH1-LD10 SoC/board supportMasahiro Yamada2015-12-215-0/+381
This is the first ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-06 14:31:49 +0000