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* arm64: dts: qcom: sm8250: switch usb1 qmp phy to USB3+DP modeDmitry Baryshkov2021-04-041-5/+18
| | | | | | | | | | USB1 QMP PHY is not just a USB3 PHY, but USB3+DP PHY. Change device tree nodes accordingly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-7-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: Add venus DT nodeBryan O'Donoghue2021-04-041-0/+59
| | | | | | | | | | | | | Add DT entries for the sm8250 venus encoder/decoder. Co-developed-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Jonathan Marek <jonathan@marek.ca> Co-developed-by: Dikshita Agarwal <dikshita@qti.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita@qti.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210401174256.1810044-3-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: Add videocc DT nodejonathan@marek.ca2021-04-041-0/+14
| | | | | | | | | | This commit adds the videocc DTS node for sm8250. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210401174256.1810044-2-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8350: Add interconnectsVinod Koul2021-04-041-0/+78
| | | | | | | | Add interconnect nodes and add them for modem and cdsp nodes Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210401113252.3078466-1-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8350: Add support for PRNG EERobert Foss2021-04-041-0/+7
| | | | | | | | | | RNG (Random Number Generator) in SM8350 features PRNG EE (Execution Environment), hence add devicetree support for it. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://lore.kernel.org/r/20210401101536.1014560-1-robert.foss@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add RPMh regulators for sc7280-idpsatya priya2021-04-041-0/+212
| | | | | | | | | | | Add regulator devices for SC7280 as RPMh regulators. This ensures that consumers are able to modify the physical state of PMIC regulators. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: satya priya <skakit@codeaurora.org> Link: https://lore.kernel.org/r/1617192339-3760-4-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845: add required clocks on the gccDmitry Baryshkov2021-04-041-0/+12
| | | | | | | | | Specify input clocks to the SDM845's Global Clock Controller as required by the bindings. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210402233944.273275-4-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8350: Add thermal zones and throttling supportRobert Foss2021-03-291-0/+826
| | | | | | | | | | | sm8350 has 29 thermal sensors split across two tsens controllers. Add the thermal zones to expose them and wireup the cpus to throttle their frequencies on crossing passive temperature thresholds. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210324124308.1265626-2-robert.foss@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8150: add i2c nodesCaleb Connolly2021-03-291-0/+521
| | | | | | | | | | Tested on the OnePlus 7 Pro (including DMA). Signed-off-by: Caleb Connolly <caleb@connolly.tech> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20210321174522.123036-3-caleb@connolly.tech Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8150: add other QUP nodes and iommusCaleb Connolly2021-03-291-0/+28
| | | | | | | | | | Add the first and third qupv3 nodes used to hook up peripherals on some devices, as well as the iommus properties for all of them. Signed-off-by: Caleb Connolly <caleb@connolly.tech> Link: https://lore.kernel.org/r/20210321174522.123036-2-caleb@connolly.tech Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: fix display nodesJonathan Marek2021-03-291-21/+6
| | | | | | | | | | | | | | | Apply these fixes to the newly added sm8250 display ndoes - Remove "notused" interconnect (which apparently was blindly copied from my old patches) - Use dispcc node example from dt-bindings, removing clocks which aren't documented or used by the driver and fixing the region size. Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes") Signed-off-by: Jonathan Marek <jonathan@marek.ca> [DB: compatibility changes split into separate patch] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210329120051.3401567-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CSDmitry Baryshkov2021-03-181-2/+3
| | | | | | | | | | | | On the GENI SPI controller is is not very efficient if the chip select line is controlled by the QUP itself (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS") for the details). Configure SPI0 CS pin as a GPIO. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210210133458.1201066-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CSDmitry Baryshkov2021-03-181-0/+100
| | | | | | | | | | | | GENI SPI controller shows several issues if it manages the CS on its own (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS")) for the details. Provide pinctrl entries for SPI controllers using the same CS pin but in GPIO mode. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210210133458.1201066-4-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: further split of spi pinctrl configDmitry Baryshkov2021-03-182-81/+148
| | | | | | | | | | | Split "default" device tree nodes into common "data-clk" nodes and "cs" nodes which might differ from board to board depending on how the slave chips are wired. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210210133458.1201066-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: split spi pinctrl configDmitry Baryshkov2021-03-182-240/+66
| | | | | | | | | | | | As discussed on linux-arm-msm list, start splitting sm8250 pinctrl settings into generic and board-specific parts. The first part to receive such treatment is the spi, so split spi pinconf to the board device tree. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210210133458.1201066-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845-db845c: Enable ov8856 sensor and connect to ISPRobert Foss2021-03-161-2/+17
| | | | | | | | | Enable camss & ov8856 DT nodes. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Andrey Konovalov <andrey.konovalov@linaro.org> Link: https://lore.kernel.org/r/20210316171931.812748-23-robert.foss@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845-db845c: Configure regulators for camss nodeRobert Foss2021-03-161-0/+4
| | | | | | | | | Add regulator to camss device tree node. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Andrey Konovalov <andrey.konovalov@linaro.org> Link: https://lore.kernel.org/r/20210316171931.812748-22-robert.foss@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845: Add CAMSS ISP nodeRobert Foss2021-03-161-0/+135
| | | | | | | | | Add the camss dt node for sdm845. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Andrey Konovalov <andrey.konovalov@linaro.org> Link: https://lore.kernel.org/r/20210316171931.812748-21-robert.foss@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pm8150: Enable RTCBjorn Andersson2021-03-123-11/+1
| | | | | | | | | | | | The PM8150 comes with everything the RTC needs, so let's just leave it enabled instead of having to explicitly enable it for all boards. In effect this patch enables the RTC on the SM8150 MTP and the SM8250 HDK. Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210106001004.4081508-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8350-mtp: Add PMICsVinod Koul2021-03-121-0/+6
| | | | | | | | | SM8350-MTP features PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B. PMICs Add the dtsi for these PMICs to MTP. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-9-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pmr735B: Add base dts fileVinod Koul2021-03-121-0/+25
| | | | | | | | Add base DTS file for PMR735B along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-8-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pmr735a: Add base dts fileVinod Koul2021-03-121-0/+25
| | | | | | | | Add base DTS file for PMR735A along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-7-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pm8350c: Add base dts fileVinod Koul2021-03-121-0/+25
| | | | | | | | Add base DTS file for PM8350C along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-6-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pm8350b: Add base dts fileVinod Koul2021-03-121-0/+25
| | | | | | | | Add base DTS file for PM8350B along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-5-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pm8350: Add base dts fileVinod Koul2021-03-121-0/+25
| | | | | | | | Add base DTS file for PM8350 along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-4-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pmk8350: Add base dts fileVinod Koul2021-03-121-0/+25
| | | | | | | | Add base DTS file for PMK8350 along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-3-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8350: Add spmi nodeVinod Koul2021-03-121-0/+18
| | | | | | | | Add SPMI node found in SM8350 SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: db845c: fix correct powerdown pin for WSA881xSrinivas Kandagatla2021-03-111-2/+2
| | | | | | | | | | | WSA881x powerdown pin is connected to GPIO1 not gpio2, so correct this. This was working so far due to a shift bug in gpio driver, however once that is fixed this will stop working, so fix this! Fixes: 89a32a4e769cc ("arm64: dts: qcom: db845c: add analog audio support") Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210309102025.28405-1-srinivas.kandagatla@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Drop duplicate dp_hot_plug_det node in trogdorStephen Boyd2021-03-111-14/+0
| | | | | | | | | | | | | | | | | | | This moved from being trogdor specific to being part of the general sc7180.dtsi SoC file in commit 681a607ad21a ("arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node"). Then we dropped the pinconf from the general sc7180.dtsi file in commit 8d079bf20410 ("arm64: dts: qcom: sc7180: Drop pinconf on dp_hot_plug_det") and added it back to the trogdor dts file in commit f772081f4883 ("arm64: dts: qcom: sc7180: Add "dp_hot_plug_det" pinconf for trogdor"). As part of this we managed to forget to drop the old copy in the trogdor dts. Let's do it now. Signed-off-by: Stephen Boyd <swboyd@chromium.org> [dianders: updated desc] Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210311131008.1.I85fc8146c0ee47e261faa0c54dd621467b81952d@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8350: fix number of pins in 'gpio-ranges'Shawn Guo2021-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-5-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: fix number of pins in 'gpio-ranges'Shawn Guo2021-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: 16951b490b20 ("arm64: dts: qcom: sm8250: Add TLMM pinctrl node") Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-4-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8150: fix number of pins in 'gpio-ranges'Shawn Guo2021-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: e13c6d144fa0 ("arm64: dts: qcom: sm8150: Add base dts file") Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-3-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845: fix number of pins in 'gpio-ranges'Shawn Guo2021-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: bc2c806293c6 ("arm64: dts: qcom: sdm845: Add gpio-ranges to TLMM node") Cc: Evan Green <evgreen@chromium.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-2-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add rpmh power-domain nodeRajendra Nayak2021-03-111-0/+47
| | | | | | | | | Add the DT node for the rpmhpd power controller on SC7280 SoCs. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615461961-17716-15-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add cpuidle statesMaulik Shah2021-03-111-0/+78
| | | | | | | | | | | | Add cpuidle states for little and big cpus. The latency values are preliminary placeholders and will be updated once testing provides the real numbers. Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615461961-17716-14-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280satya priya2021-03-111-0/+18
| | | | | | | | | | Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus. Signed-off-by: satya priya <skakit@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1615461961-17716-13-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add APSS watchdog nodeSai Prakash Ranjan2021-03-111-0/+7
| | | | | | | | | | | Add APSS (Application Processor Subsystem) watchdog DT node for SC7280 SoC. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615461961-17716-12-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add reserved memory for fwMaulik Shah2021-03-111-0/+10
| | | | | | | | | | Add fw reserved memory area for CPUCP (CPUSS control processor) and AOP (Always ON processor) Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1615461961-17716-10-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add device node for APPS SMMUSai Prakash Ranjan2021-03-111-0/+89
| | | | | | | | | | | Adding device node for APPS SMMU available on SC7280 chipset. This is shared among the multiple client devices such as display, video, usb, mmc and others. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1615461961-17716-9-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: SC7280: Add rpmhcc clock controller nodeRajendra Nayak2021-03-111-0/+16
| | | | | | | | | | | Add rpmhcc clock controller node for SC7280. Also add references to rpmhcc clocks in gcc. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615461961-17716-7-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add RSC and PDC devicesMaulik Shah2021-03-111-0/+44
| | | | | | | | | | Add PDC interrupt controller along with apps RSC device. Also add reserved memory for command_db. Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1615461961-17716-6-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add basic dts/dtsi files for sc7280 socRajendra Nayak2021-03-113-0/+347
| | | | | | | | | | Add initial device tree support for the sc7280 SoC and the IDP boards based on this SoC Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615461961-17716-4-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: Introduce SM8350 HDKBjorn Andersson2021-03-112-0/+320
| | | | | | | | | | | | Add initial DTS for the Snapdragon 888 Mobile Hardware Development Kit, aka SM8350 HDK. This initial version describes debug UART, UFS storage, the three USB connectors and remoteprocs. Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210308182113.1284966-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8994: don't use empty memory nodeVinod Koul2021-03-111-2/+2
| | | | | | | | | | | | We expect bootloader to full memory details but passing empty values gives warning, so add a default value arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0, 0, 0]]} Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210308060826.3074234-5-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8916: don't use empty memory nodeVinod Koul2021-03-111-2/+2
| | | | | | | | | | | | We expect bootloader to full memory details but passing empty values gives warning, so add a default value arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0, 0, 0]]} Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210308060826.3074234-3-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: apq8016-sbc: drop qcom,sbcVinod Koul2021-03-111-1/+1
| | | | | | | | | | | | | | | | | | apq8016-sbc is one of the compaitibles for this board, but is not documented, so drop it. This fixes these two warns: arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible: ['qcom,apq8016-sbc', 'qcom,apq8016', 'qcom,sbc'] is not valid under any of the given schemas (Possible causes of the failure): arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible: ['qcom,apq8016-sbc', 'qcom,apq8016', 'qcom,sbc'] is too long arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible:0: 'qcom,apq8016-sbc' is not one of ['qcom,apq8064-cm-qs600', 'qcom,apq8064-ifc6410'] arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible:0: 'qcom,apq8016-sbc' is not one of ['qcom,apq8074-dragonboard'] Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210308060826.3074234-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Avoid glitching SPI CS at bootup on trogdorDouglas Anderson2021-03-111-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At boot time the following happens: 1. Device core gets ready to probe our SPI driver. 2. Device core applies SPI controller's "default" pinctrl. 3. Device core calls the SPI driver's probe() function which will eventually setup the chip select GPIO as "unasserted". Thinking about the above, we can find: a) For SPI devices that the BIOS inits (Cr50 and EC), the BIOS would have had them configured as "GENI" pins and not as "GPIO" pins. b) It turns out that our BIOS also happens to init these pins as "output" (even though it doesn't need to since they're not muxed as GPIO) but leaves them at the default state of "low". c) As soon as we apply the "default" chip select it'll switch the function to GPIO and stop driving the chip select high (which is how "GENI" was driving it) and start driving it low. d) As of commit 9378f46040be ("UPSTREAM: spi: spi-geni-qcom: Use the new method of gpio CS control"), when the SPI core inits things it inits the GPIO to be "deasserted". Prior to that commit the GPIO was left untouched until first use. e) When the first transaction happens we'll assert the chip select and then deassert it after done. So before the commit to change us to use gpio descriptors we used to have a _really long_ assertion of chip select before our first transaction (because it got pulled down and then the first "assert" was a no-op). That wasn't great but (apparently) didn't cause any real harm. After the commit to change us to use gpio descriptors we end up glitching the chip select line during probe. It would go low and then high with no data transferred. The other side ought to be robust against this, but it certainly could cause some confusion. It's known to at least cause an error message on the EC console and it's believed that, under certain timing conditions, it could be getting the EC into a confused state causing the EC driver to fail to probe. Let's fix things to avoid the glitch. We'll add an extra pinctrl entry that sets the value of the pin to output high (CS deasserted) before doing anything else. We'll do this in its own pinctrl node that comes before the normal pinctrl entries to ensure that the order is correct and that this gets applied before the mux change. This change is in the trogdor board file rather than in the SoC dtsi file because chip select polarity can be different depending on what's hooked up and it doesn't feel worth it to spam the SoC dtsi file with both options. The board file would need to pick the right one anyway. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: cfbb97fde694 ("arm64: dts: qcom: Switch sc7180-trogdor to control SPI CS via GPIO") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210218145456.1.I1da01a075dd86e005152f993b2d5d82dd9686238@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Use pdc interrupts for USB instead of GIC interruptsSandeep Maheswaram2021-03-111-4/+4
| | | | | | | | | | Using pdc interrupts for USB instead of GIC interrupts to support wake up in case xo shutdown. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Link: https://lore.kernel.org/r/1594235417-23066-4-git-send-email-sanm@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: Add sc7180-trogdor-coachz skusDouglas Anderson2021-03-116-0/+449
| | | | | | | | | | | | | | | | | | | This is a trogdor variant. This is mostly a grab from the downstream tree with notable exceptions: - I skip -rev0. This was a super early build and there's no advantage of long term support. - I remove sound node since sound hasn't landed upstream yet. Cc: Gwendal Grignou <gwendal@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.13.I3d1f5f8a3bf31e8014229df0d4cfdff20e9cc90f@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: Add sc7180-trogdor-pompom skusDouglas Anderson2021-03-116-0/+390
| | | | | | | | | | | | | | | | | | | | | | | | | | This is a trogdor variant. This is mostly a grab from the downstream tree with notable exceptions: - I skip -rev0. This was a super early build and there's no advantage of long term support. - In -rev1 I translate the handling of the USB hub like is done for similar boards. See the difference between the downstream and upstream 'sc7180-trogdor-lazor-r0.dts' for an example. This will need to be resolved when proper support for the USB hub is figured out upstream. - I remove sound node since sound hasn't landed upstream yet. - In incorporate the pending <https://crrev.com/c/2719075> for the keyboard. Cc: Philip Chen <philipchen@google.com> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.12.If93a01b30d20dccacbad4be8ddc519dc20a51a1e@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 13:30:10 +0000