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* Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2016-08-0219-179/+161
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull KVM updates from Paolo Bonzini: - ARM: GICv3 ITS emulation and various fixes. Removal of the old VGIC implementation. - s390: support for trapping software breakpoints, nested virtualization (vSIE), the STHYI opcode, initial extensions for CPU model support. - MIPS: support for MIPS64 hosts (32-bit guests only) and lots of cleanups, preliminary to this and the upcoming support for hardware virtualization extensions. - x86: support for execute-only mappings in nested EPT; reduced vmexit latency for TSC deadline timer (by about 30%) on Intel hosts; support for more than 255 vCPUs. - PPC: bugfixes. * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (302 commits) KVM: PPC: Introduce KVM_CAP_PPC_HTM MIPS: Select HAVE_KVM for MIPS64_R{2,6} MIPS: KVM: Reset CP0_PageMask during host TLB flush MIPS: KVM: Fix ptr->int cast via KVM_GUEST_KSEGX() MIPS: KVM: Sign extend MFC0/RDHWR results MIPS: KVM: Fix 64-bit big endian dynamic translation MIPS: KVM: Fail if ebase doesn't fit in CP0_EBase MIPS: KVM: Use 64-bit CP0_EBase when appropriate MIPS: KVM: Set CP0_Status.KX on MIPS64 MIPS: KVM: Make entry code MIPS64 friendly MIPS: KVM: Use kmap instead of CKSEG0ADDR() MIPS: KVM: Use virt_to_phys() to get commpage PFN MIPS: Fix definition of KSEGX() for 64-bit KVM: VMX: Add VMCS to CPU's loaded VMCSs before VMPTRLD kvm: x86: nVMX: maintain internal copy of current VMCS KVM: PPC: Book3S HV: Save/restore TM state in H_CEDE KVM: PPC: Book3S HV: Pull out TM state save/restore into separate procedures KVM: arm64: vgic-its: Simplify MAPI error handling KVM: arm64: vgic-its: Make vgic_its_cmd_handle_mapi similar to other handlers KVM: arm64: vgic-its: Turn device_id validation into generic ID validation ...
| * KVM: arm64: vgic-its: Enable ITS emulation as a virtual MSI controllerAndre Przywara2016-07-183-0/+8
| | | | | | | | | | | | | | | | | | | | | | Now that all ITS emulation functionality is in place, we advertise MSI functionality to userland and also the ITS device to the guest - if userland has configured that. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * KVM: arm64: vgic-its: Introduce new KVM ITS deviceAndre Przywara2016-07-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a new KVM device that represents an ARM Interrupt Translation Service (ITS) controller. Since there can be multiple of this per guest, we can't piggy back on the existing GICv3 distributor device, but create a new type of KVM device. On the KVM_CREATE_DEVICE ioctl we allocate and initialize the ITS data structure and store the pointer in the kvm_device data. Upon an explicit init ioctl from userland (after having setup the MMIO address) we register the handlers with the kvm_io_bus framework. Any reference to an ITS thus has to go via this interface. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * KVM: arm/arm64: Extend arch CAP checks to allow per-VM capabilitiesAndre Przywara2016-07-182-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | KVM capabilities can be a per-VM property, though ARM/ARM64 currently does not pass on the VM pointer to the architecture specific capability handlers. Add a "struct kvm*" parameter to those function to later allow proper per-VM capability reporting. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: Clean up a conditionDan Carpenter2016-07-141-2/+2
| | | | | | | | | | | | | | | | My static checker complains that this condition looks like it should be == instead of =. This isn't a fast path, so we don't need to be fancy. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm/arm64: Get rid of KERN_TO_HYPMarc Zyngier2016-07-031-1/+0
| | | | | | | | | | | | | | | | We have both KERN_TO_HYP and kern_hyp_va, which do the exact same thing. Let's standardize on the latter. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm/arm64: KVM: Prune unused #definesMarc Zyngier2016-07-031-10/+0
| | | | | | | | | | | | | | | | We can now remove a number of dead #defines, thanks to the trampoline code being gone. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm: KVM: Allow hyp teardownMarc Zyngier2016-07-031-1/+2
| | | | | | | | | | | | | | | | | | | | | | So far, KVM was getting in the way of kexec on 32bit (and the arm64 kexec hackers couldn't be bothered to fix it on 32bit...). With simpler page tables, tearing KVM down becomes very easy, so let's just do it. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm/arm64: KVM: Kill free_boot_hyp_pgdMarc Zyngier2016-07-031-1/+0
| | | | | | | | | | | | | | | | There is no way to free the boot PGD, because it doesn't exist anymore as a standalone entity. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm/arm64: KVM: Drop boot_pgdMarc Zyngier2016-07-032-5/+2
| | | | | | | | | | | | | | | | | | Since we now only have one set of page tables, the concept of boot_pgd is useless and can be removed. We still keep it as an element of the "extended idmap" thing. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm64: KVM: Simplify HYP init/teardownMarc Zyngier2016-07-035-92/+26
| | | | | | | | | | | | | | | | | | Now that we only have the "merged page tables" case to deal with, there is a bunch of things we can simplify in the HYP code (both at init and teardown time). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm/arm64: KVM: Always have merged page tablesMarc Zyngier2016-07-031-24/+7
| | | | | | | | | | | | | | | | | | | | We're in a position where we can now always have "merged" page tables, where both the runtime mapping and the idmap coexist. This results in some code being removed, but there is more to come. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm64: KVM: Runtime detection of lower HYP offsetMarc Zyngier2016-07-031-0/+19
| | | | | | | | | | | | | | Add the code that enables the switch to the lower HYP VA range. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm/arm64: KVM: Export __hyp_text_start/end symbolsMarc Zyngier2016-07-031-0/+4
| | | | | | | | | | | | | | | | Declare the __hyp_text_start/end symbols in asm/virt.h so that they can be reused without having to declare them locally. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm64: KVM: Refactor kern_hyp_va to deal with multiple offsetsMarc Zyngier2016-07-032-14/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we move towards a selectable HYP VA range, it is obvious that we don't want to test a variable to find out if we need to use the bottom VA range, the top VA range, or use the address as is (for VHE). Instead, we can expand our current helper to generate the right mask or nop with code patching. We default to using the top VA space, with alternatives to switch to the bottom one or to nop out the instructions. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm64: KVM: Define HYP offset masksMarc Zyngier2016-07-031-2/+6
| | | | | | | | | | | | | | | | | | Define the two possible HYP VA regions in terms of VA_BITS, and keep HYP_PAGE_OFFSET_MASK as a temporary compatibility definition. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm64: Add ARM64_HYP_OFFSET_LOW capabilityMarc Zyngier2016-07-031-1/+2
| | | | | | | | | | | | | | | | | | As we need to indicate to the rest of the kernel which region of the HYP VA space is safe to use, add a capability that will indicate that KVM should use the [VA_BITS-2:0] range. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm64: KVM: Kill HYP_PAGE_OFFSETMarc Zyngier2016-07-031-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | HYP_PAGE_OFFSET is not massively useful. And the way we use it in KERN_HYP_VA is inconsistent with the equivalent operation in EL2, where we use a mask instead. Let's replace the uses of HYP_PAGE_OFFSET with HYP_PAGE_OFFSET_MASK, and get rid of the pointless macro. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm/arm64: KVM: Remove hyp_kern_va helperMarc Zyngier2016-07-031-12/+0
| | | | | | | | | | | | | | hyp_kern_va is now completely unused, so let's remove it entirely. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm64: KVM: Always reference __hyp_panic_string via its kernel VAMarc Zyngier2016-07-031-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | __hyp_panic_string is passed via the HYP panic code to the panic function, and is being "upgraded" to a kernel address, as it is referenced by the HYP code (in a PC-relative way). This is a bit silly, and we'd be better off obtaining the kernel address and not mess with it at all. This patch implements this with a tiny bit of asm glue, by forcing the string pointer to be read from the literal pool. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm64: KVM: Merged page tables documentationMarc Zyngier2016-07-031-3/+37
| | | | | | | | | | | | | | | | | | Since dealing with VA ranges tends to hurt my brain badly, let's start with a bit of documentation that will hopefully help understanding what comes next... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: arm/arm64: The GIC is dead, long live the GICMarc Zyngier2016-07-032-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I don't think any single piece of the KVM/ARM code ever generated as much hatred as the GIC emulation. It was written by someone who had zero experience in modeling hardware (me), was riddled with design flaws, should have been scrapped and rewritten from scratch long before having a remote chance of reaching mainline, and yet we supported it for a good three years. No need to mention the names of those who suffered, the git log is singing their praises. Thankfully, we now have a much more maintainable implementation, and we can safely put the grumpy old GIC to rest. Fellow hackers, please raise your glass in memory of the GIC: The GIC is dead, long live the GIC! Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm/arm64: KVM: Make default HYP mappings non-excutableMarc Zyngier2016-06-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | Structures that can be generally written to don't have any requirement to be executable (quite the opposite). This includes the kvm and vcpu structures, as well as the stacks. Let's change the default to incorporate the XN flag. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm/arm64: KVM: Map the HYP text as read-onlyMarc Zyngier2016-06-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | There should be no reason for mapping the HYP text read/write. As such, let's have a new set of flags (PAGE_HYP_EXEC) that allows execution, but makes the page as read-only, and update the two call sites that deal with mapping code. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm/arm64: KVM: Enforce HYP read-only mapping of the kernel's rodata sectionMarc Zyngier2016-06-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | In order to be able to use C code in HYP, we're now mapping the kernel's rodata in HYP. It works absolutely fine, except that we're mapping it RWX, which is not what it should be. Add a new HYP_PAGE_RO protection, and pass it as the protection flags when mapping the rodata section. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm64: Add PTE_HYP_XN page table flagMarc Zyngier2016-06-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | EL2 page tables can be configured to deny code from being executed, which is done by setting bit 54 in the page descriptor. It is the same bit as PTE_UXN, but the "USER" reference felt odd in the hypervisor code. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * arm/arm64: KVM: Add a protection parameter to create_hyp_mappingsMarc Zyngier2016-06-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | Currently, create_hyp_mappings applies a "one size fits all" page protection (PAGE_HYP). As we're heading towards separate protections for different sections, let's make this protection a parameter, and let the callers pass their prefered protection (PAGE_HYP for everyone for the time being). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
| * KVM: ARM64: Fix typosAndrea Gelmini2016-06-143-3/+3
| | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | Merge tag 'armsoc-dt64' of ↵Linus Torvalds2016-08-0150-139/+4413
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull 64-bit ARM DT updates from Olof Johansson: "Just as the 32-bit contents, the 64-bit device tree branch also contains a number of additions this release cycle. New platforms: - LG LG1313 - Mediatek MT6755 - Renesas r8a7796 - Broadcom 2837 Other platforms with larger updates are: - Nvidia X1 platforms (USB 3.0, regulators, display subsystem) - Mediatek MT8173 (display subsystem added) - Rockchip RK3399 (a lot of new peripherals) - ARM Juno reference implementation (SCPI power domains, coresight, thermal)" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits) arm64: tegra: Enable HDMI on Jetson TX1 arm64: tegra: Add sor1_src clock arm64: tegra: Add XUSB powergates on Tegra210 arm64: tegra: Add DPAUX pinctrl bindings arm64: tegra: Add ACONNECT bus node for Tegra210 arm64: tegra: Add audio powergate node for Tegra210 arm64: tegra: Add regulators for Tegra210 Smaug arm64: tegra: Correct Tegra210 XUSB mailbox interrupt arm64: tegra: Enable XUSB controller on Jetson TX1 arm64: tegra: Enable debug serial on Jetson TX1 arm64: tegra: Add Tegra210 XUSB controller arm64: tegra: Add Tegra210 XUSB pad controller arm64: tegra: Add DSI panel on Jetson TX1 arm64: tegra: p2597: Add SDMMC power supplies arm64: tegra: Add PMIC support on Jetson TX1 Revert "ARM64: DTS: meson-gxbb: switch ethernet to real clock" arm64: dts: hi6220: Add pl031 RTC support arm64: dts: r8a7796/salvator-x: Enable watchdog timer arm64: dts: r8a7796: Add RWDT node arm64: dts: r8a7796: Use SYSC "always-on" PM Domain ...
| * \ Merge tag 'tegra-for-4.8-arm64-dt' of ↵Arnd Bergmann2016-07-145-1/+1218
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/late Merge "arm64: tegra: Device tree changes for v4.8-rc1" from Thierry Reding: A slew of updates for Tegra210 support: PMIC and regulator additions, which in turn allow a bunch of features to be enabled. Some assemblies of the Jetson TX1 come with a DSI panel that is now supported. For all other assemblies, this set of changes enables the HDMI output. Jetson TX1 can now also make use of the XUSB controller. PMIC and regulator support is also added for Smaug, which will allow a number of interesting feature additions in future releases. * tag 'tegra-for-4.8-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Enable HDMI on Jetson TX1 arm64: tegra: Add sor1_src clock arm64: tegra: Add XUSB powergates on Tegra210 arm64: tegra: Add DPAUX pinctrl bindings arm64: tegra: Add ACONNECT bus node for Tegra210 arm64: tegra: Add audio powergate node for Tegra210 arm64: tegra: Add regulators for Tegra210 Smaug arm64: tegra: Correct Tegra210 XUSB mailbox interrupt arm64: tegra: Enable XUSB controller on Jetson TX1 arm64: tegra: Enable debug serial on Jetson TX1 arm64: tegra: Add Tegra210 XUSB controller arm64: tegra: Add Tegra210 XUSB pad controller arm64: tegra: Add DSI panel on Jetson TX1 arm64: tegra: p2597: Add SDMMC power supplies arm64: tegra: Add PMIC support on Jetson TX1
| | * | arm64: tegra: Enable HDMI on Jetson TX1Thierry Reding2016-07-141-0/+35
| | | | | | | | | | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Add sor1_src clockThierry Reding2016-07-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The sor1 IP block needs the sor1_src clock to configure the clock tree depending on whether it's running in HDMI or DP mode. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Add XUSB powergates on Tegra210Jon Hunter2016-07-141-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra210 XUSB subsystem has 3 power partitions which are XUSBA (super-speed logic), XUSBB (USB device logic) and XUSBC (USB host logic). Populate the device-tree nodes for these XUSB partitions. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Add DPAUX pinctrl bindingsJon Hunter2016-07-141-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the DPAUX pinctrl states for the DPAUX nodes defining all three possible states of "aux", "i2c" and "off". Also add the 'i2c-bus' node for the DPAUX nodes so that the I2C driver core does not attempt to parse the pinctrl state nodes. Populate the nodes for the pinctrl clients of the DPAUX pin controller. There are two clients for each DPAUX instance, namely the SOR and one of the I2C adapters. The SOR clients may used the DPAUX pins in either AUX or I2C modes and so for these devices we don't define any of the generic pinctrl states (default, idle, etc) because the SOR driver will directly set the state needed. For I2C clients only the I2C mode is used and so we can simplify matters by using the generic pinctrl states for default and idle. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Add ACONNECT bus node for Tegra210Jon Hunter2016-07-141-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the ACONNECT bus node for Tegra210 which is used to interface to the various devices in the Audio Processing Engine (APE). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Add audio powergate node for Tegra210Jon Hunter2016-07-141-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the audio powergate for Tegra210. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Add regulators for Tegra210 SmaugRhyland Klein2016-07-141-0/+314
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add regulators to the Tegra210 Smaug DTS file including support for the MAX77620 PMIC. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Correct Tegra210 XUSB mailbox interruptJon Hunter2016-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for the XUSB pad controller. For some Tegra210 boards, this is causing USB connect and disconnect events to go undetected. Fix this by changing the interrupt number for the XUSB mailbox to 40. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Enable XUSB controller on Jetson TX1Thierry Reding2016-07-141-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the XUSB controller on Jetson TX1. One of the USB 3.0 lanes goes to an internal ethernet interface, while a second USB 3.0 lane supports the USB-A receptacle on the I/O board. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Enable debug serial on Jetson TX1Thierry Reding2016-07-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a chosen node to the device tree that contains a stdout-path property which defines the debug serial port. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Add Tegra210 XUSB controllerThierry Reding2016-07-141-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a device tree node for the Tegra XUSB controller. It contains a phandle to the XUSB pad controller for control of the PHYs assigned to the USB ports. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Add Tegra210 XUSB pad controllerThierry Reding2016-07-141-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | Add a device tree node for the XUSB pad controller found on Tegra210. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Add DSI panel on Jetson TX1Thierry Reding2016-07-142-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some variants of the Jetson TX1 ship with a 8.0" WUXGA TFT LCD panel connected via four DSI lanes. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: p2597: Add SDMMC power suppliesThierry Reding2016-07-141-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add power supplies for the SD/MMC card slot. Note that vmmc-supply is currently restricted to 3.3 V because we don't support switching the mode yet. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | arm64: tegra: Add PMIC support on Jetson TX1Thierry Reding2016-07-142-0/+300
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a device tree node for the MAX77620 PMIC found on the p2180 processor module (Jetson TX1). Also add supporting power supplies, such as the main 5 V system supply. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | Merge tag 'hi6220-dt-for-4.8-2' of git://github.com/hisilicon/linux-hisi ↵Arnd Bergmann2016-07-141-0/+16
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/late Merge "ARM64: DT: Hisilicon Hi6220 updates for 4.8" from Wei Xu: - Add pl031 rtc0 and rtc1 support for hi6220 SoC * tag 'hi6220-dt-for-4.8-2' of git://github.com/hisilicon/linux-hisi: arm64: dts: hi6220: Add pl031 RTC support clk: hi6220: Add RTC clock for pl031
| | * | | arm64: dts: hi6220: Add pl031 RTC supportZhangfei Gao2016-07-071-0/+16
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pl031 rtc0 and rtc1 support to hi6220 dtsi Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> [jstultz: Forward ported and tweaked commit description, added rtc1 entry as suggested by Guodong] Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | | Merge tag 'samsung-dt64-4.8-2' of ↵Arnd Bergmann2016-07-141-1/+1
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64 Merge "Samsung DeviceTree changes for ARM64 for v4.8" from Krzysztof Kozlowski: 1. Adjust the voltage of CPU buck regulator so scaling could work. * tag 'samsung-dt64-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: Modify the voltage range for BUCK2 for exynos7
| | * | | arm64: dts: exynos: Modify the voltage range for BUCK2 for exynos7Abhilash Kesavan2016-07-061-1/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the BUCK2 (vdd_atlas) voltage range to '500 - 1200mv' since CPU DVFS requires it. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * | | Merge tag 'juno-dt-4.8' of ↵Arnd Bergmann2016-07-144-0/+461
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64 Merge "Juno platform DT updates for v4.8" from Sudeep Holla: 1. Adds various CoreSight debug components on Juno boards 2. Adds SCPI device power domains and use them for coresight components 3. Adds thermal zones for SCPI sensors on Juno * tag 'juno-dt-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: add thermal zones for scpi sensors arm64: dts: juno: add SCPI power domains for device power management arm64: dts: juno: add coresight support
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