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| | * | | | | | | | | | | | | arm64: tegra: Add Jetson Nano SC7 timingsSowjanya Komatineni2019-10-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add platform specific SC7 timing configuration to the Jetson Nano device tree. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Add Jetson TX1 SC7 timingsSowjanya Komatineni2019-10-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add platform specific SC7 timing configuration to the Jetson TX1 device tree. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Enable wake from deep sleep on RTC alarmSowjanya Komatineni2019-10-291-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates device tree for RTC and PMC to allow system wake from deep sleep on RTC alarm. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Add PMU on Tegra210Thierry Reding2019-10-291-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NVIDIA Tegra210 contains an ARM PMU v3 that can be used to gather statistics about the processors and their memory system. Add a device tree node so that this functionality can be exposed. Reported-by: William Cohen <giantklein@gmail.com> Tested-by: William Cohen <giantklein@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Add blank lines for better readabilityThierry Reding2019-10-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Separate the individual thermal zones by a blank line for improved readability. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Enable DisplayPort on Jetson AGX XavierThierry Reding2019-10-291-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable both USB-C/DP ports on Jetson AGX Xavier and wire up the power supplies for the SORs that drive these outputs. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: p2888: Rename regulators for consistencyThierry Reding2019-10-291-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the PMIC regulators had names that don't match the schematics. Rename them so that it is easier to cross-reference with the hardware documentation. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Enable DP support on Jetson TX2Thierry Reding2019-10-291-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If equipped with an E3320 display module, Jetson TX2 can support DisplayPort. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Fix compatible for SOR1Thierry Reding2019-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that both SORs on Tegra186 are the same, so there's no need to distinguish between them in the compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Enable DP support on Jetson NanoThierry Reding2019-10-291-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the AVDD_IO_EDP_1V05 and enable the SOR and DPAUX hardware blocks that are used to drive DisplayPort on Jetson Nano. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Add SOR0_OUT clock on Tegra210Thierry Reding2019-10-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock was not previously used because it is a fixed clock. However, adding it here allows operating systems to deal with SOR0 the same way as SOR1. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Assume no CLKREQ presence by defaultVidya Sagar2019-10-291-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although Tegra194 has support for CLKREQ sideband signal and P2972 has routing of the same till the slot, it is the case most of the time that the connected device doesn't have CLKREQ support. Hence, it makes sense to assume that there is no CLKREQ support by default and it can be enabled on need basis when a card with CLKREQ support is connected. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Enable SMMU for VIC on Tegra186Thierry Reding2019-10-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable address translation for VIC via the SMMU on Tegra186. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Enable XUSB host controller on Jetson TX2Nagarjuna Kristam2019-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables the use of the USB ports found on the Jetson TX2 for input or external storage, for example. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Enable SMMU for XUSB host on Tegra186Nagarjuna Kristam2019-10-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling the SMMU for XUSB host allows buffers to be mapped through the ARM SMMU, which helps protecting the system from rogue memory accesses by the XUSB host. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Enable XUSB pad controller on Jetson TX2Nagarjuna Kristam2019-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The XUSB pad controller is a prerequisite for enabling XUSB support. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Add ethernet alias on Jetson AGX XavierThierry Reding2019-10-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra194 EQOS controller is used as primary Ethernet interface. Set the ethernet0 alias to reflect that. Generic bootloader code can use this to find the primary Ethernet device and set the MAC address, for example. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Fix compatible string for EQOS on Tegra194Thierry Reding2019-10-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EQOS Ethernet controller found on Tegra194 is compatible with its predecessor or Tegra186. However, it is an established practice to add a compatible string for the most recent generation of the SoC as well, just in case some incompatibilities or bugs are later discovered. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Hook up edp interrupt on Tegra210 SOCTHERMThierry Reding2019-10-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason this was never hooked up. Do it now so that over-current interrupts can be logged. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Fix base address for SOR1 on Tegra194Thierry Reding2019-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SOR1 hardware block's registers start at physical address 0x15b40000 as correctly specified by the unit-address, but the reg property lists a wrong value, likely because it was copy-and-pasted from SOR0 but not correctly updated. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Add unit-address for ACONNECT on Tegra194Thierry Reding2019-10-292-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ACONNECT complex starts at physical address 0x2900000, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Add unit-address for CBB on Tegra194Thierry Reding2019-10-293-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The control back-bone (CBB) starts at physical address 0, so give it a unit-address to comply with standard naming practices checked for by the device tree compiler. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Add CPU and cache topology for Tegra194Thierry Reding2019-10-291-12/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra194 has four CPU clusters, each with their own cache hierarchy. This patch creates the CPU map for these clusters and adds the second- and third-level caches and associates them with the CPUs. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Fix 'active-low' warning for Jetson Xavier regulatorJon Hunter2019-10-291-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information in p2972-0000 platform") added regulators for the PCIe slot on the Jetson Xavier platform. One of these regulators has an active-low enable and this commit incorrectly added an active-low specifier for the GPIO which causes the following warning to occur on boot ... WARNING KERN regulator@3 GPIO handle specifies active low - ignored The fixed-regulator binding does not use the active-low flag from the gpio specifier and purely relies of the presence of the 'enable-active-high' property to determine if it is active high or low (if this property is omitted). Fix this warning by setting the GPIO to active-high in the GPIO specifier. Finally, remove the 'enable-active-low' as this is not a valid property. Fixes: 4fdbfd60a3a2 ("arm64: tegra: Add PCIe slot supply information in p2972-0000 platform") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | | | | | arm64: tegra: Fix 'active-low' warning for Jetson TX1 regulatorJon Hunter2019-10-291-1/+1
| | |/ / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 34993594181d ("arm64: tegra: Enable HDMI on Jetson TX1") added a regulator for HDMI on the Jetson TX1 platform. This regulator has an active high enable, but the GPIO specifier for enabling the regulator incorrectly defines it as active-low. This causes the following warning to occur on boot ... WARNING KERN regulator@10 GPIO handle specifies active low - ignored The fixed-regulator binding does not use the active-low flag from the gpio specifier and purely relies of the presence of the 'enable-active-high' property to determine if it is active high or low (if this property is omitted). Fix this warning by setting the GPIO to active-high in the GPIO specifier which aligns with the presense of the 'enable-active-high' property. Fixes: 34993594181d ("arm64: tegra: Enable HDMI on Jetson TX1") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | | | | | | | | | | | Merge tag 'sunxi-dt-for-5.5-1' of ↵Olof Johansson2019-11-0311-0/+165
| |\ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|/ / / / / / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Our usual bunch of DT patches, with this time mostly: - Mali GPU support for the H6 - Two new crypto drivers enablement - A few fixes to our DTs, fixed through the validation effort - New boards: NanoPi Duo2 * tag 'sunxi-dt-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (22 commits) dt-bindings: arm: sunxi: add FriendlyARM NanoPi Duo2 ARM: dts: sun8i: add FriendlyARM NanoPi Duo2 arm64: allwinner: h6: Enable GPU node for Tanix TX6 arm64: dts: allwinner: bluetooth for Emlid Neutis N5 ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pins ARM: dts: sun9i: a80: Add Security System node ARM: dts: sun8i: a83t: Add Security System node arm64: dts: allwinner: sun50i: Add Crypto Engine node on H6 arm64: dts: allwinner: sun50i: Add crypto engine node on H5 arm64: dts: allwinner: sun50i: Add Crypto Engine node on A64 ARM: dts: sun8i: H3: Add Crypto Engine node ARM: dts: sun8i: R40: add crypto engine node dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine arm64: dts: allwinner: Add mali GPU supply for H6 boards arm64: dts: allwinner: Add ARM Mali GPU node for H6 ARM: dts: sun8i: a83t: a711: Add touchscreen node ARM: dts: sun5i: olinuxino micro: Fix AT24 node name ARM: dts: sun9i: Add missing watchdog clocks arm64: dts: sun50i: sopine-baseboard: Expose serial1, serial2 and serial3 arm64: dts: allwinner: orange-pi-3: Enable UART1 / Bluetooth ... Link: https://lore.kernel.org/r/1bf18c83-f41d-4353-9ca2-9585b8693df2.lettre@localhost Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | | | | | arm64: allwinner: h6: Enable GPU node for Tanix TX6Clément Péron2019-11-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike other H6 boards, Tanix TX6 doesn't have a PMIC so we can enable the GPU without providing a specific power supply. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | | | | | arm64: dts: allwinner: bluetooth for Emlid Neutis N5Georgii Staroselskii2019-11-011-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Emlid Neutis N5 board has AP6212 BT+WiFi chip. This patch is in line with 8558c6e21ceb ("ARM: dts: sun8i: h3: bluetooth for Banana Pi M2 Zero board") and other commits that add Bluetooth support for similar boards. Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | | | | | arm64: dts: allwinner: sun50i: Add Crypto Engine node on H6Corentin Labbe2019-11-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. This patch enables the Crypto Engine on the Allwinner H6 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | | | | | arm64: dts: allwinner: sun50i: Add crypto engine node on H5Corentin Labbe2019-11-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner H5 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | | | | | arm64: dts: allwinner: sun50i: Add Crypto Engine node on A64Corentin Labbe2019-11-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner A64 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | | | | | arm64: dts: allwinner: Add mali GPU supply for H6 boardsClément Péron2019-10-314-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable and add supply to the Mali GPU node on all the H6 boards. Regarding the datasheet the maximum time for supply to reach its voltage is 32ms. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | | | | | arm64: dts: allwinner: Add ARM Mali GPU node for H6Clément Péron2019-10-311-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the mali gpu node to the H6 device-tree. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | | | | | arm64: dts: sun50i: sopine-baseboard: Expose serial1, serial2 and serial3Alistair Francis2019-10-211-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow what the sun50i-a64-pine64.dts does and expose all 5 serial connections. Signed-off-by: Alistair Francis <alistair@alistair23.me> Signed-off-by: Maxime Ripard <mripard@kernel.org>
| | * | | | | | | | | | | | arm64: dts: allwinner: orange-pi-3: Enable UART1 / BluetoothOndrej Jirman2019-10-081-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board contains AP6256 WiFi/BT module that has its bluetooth part connected to SoC's UART1 port. Enable this port, and add node for the bluetooth device. Bluetooth part is named bcm4345c5. You'll need a BCM4345C5.hcd firmware file that can be found in the Xulongs's repository for H6: https://github.com/orangepi-xunlong/OrangePiH6_external/tree/master/ap6256 The driver expects the firmware at the following path relative to the firmware directory: brcm/BCM4345C5.hcd Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Maxime Ripard <mripard@kernel.org>
| | * | | | | | | | | | | | arm64: dts: allwinner: h6: Add pin configs for uart1Ondrej Jirman2019-10-081-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Orange Pi 3 uses UART1 for bluetooth. Add pinconfigs so that we can use them. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Maxime Ripard <mripard@kernel.org>
| | * | | | | | | | | | | | arm64: dts: allwinner: a64: orangepi-win: Enable audio codecJernej Skrabec2019-10-071-0/+29
| | |/ / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables internal audio codec on OrangePi Win board by enabling all relevant nodes and adding appropriate routing. Board has on-board microphone (MIC1) and 3.5 mm jack with stereo audio and microphone (MIC2). Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <mripard@kernel.org>
| * | | | | | | | | | | | arm64: dts: lg1313: DT fix s/#interrupts-cells/#interrupt-cells/Geert Uytterhoeven2019-11-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The standard DT property is called "#interrupt-cells". Link: https://lore.kernel.org/r/20191101160356.32034-2-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Chanho Min <chanho.min@lge.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | | | | | | | | | arm64: dts: lg1312: DT fix s/#interrupts-cells/#interrupt-cells/Geert Uytterhoeven2019-11-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The standard DT property is called "#interrupt-cells". Link: https://lore.kernel.org/r/20191101160356.32034-1-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chanho Min <chanho.min@lge.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | | | | | | | | | Merge tag 'renesas-arm64-dt-for-v5.5-tag2' of ↵Olof Johansson2019-11-039-2/+1276
| |\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM64 DT updates for v5.5 (take two) - Video-Input and Serial-ATA support on RZ/G2N, - Color Management Module support on various R-Car Gen3 SoCs, - Initial support for the R-Car M3-W+ (r8a77961) SoC on the Salvator-XS board. * tag 'renesas-arm64-dt-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+ arm64: dts: renesas: Add Renesas R8A77961 SoC support arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960 dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions dt-bindings: power: Add r8a77961 SYSC power domain definitions arm64: dts: renesas: r8a774b1: Add SATA controller node arm64: dts: renesas: rcar-gen3: Add CMM units arm64: dts: renesas: r8a774b1: Add VIN and CSI-2 support Link: https://lore.kernel.org/r/20191101155842.31467-5-geert+renesas@glider.be Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | | | | | arm64: dts: renesas: Add support for Salvator-XS with R-Car M3-W+Geert Uytterhoeven2019-11-012-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for the Renesas Salvator-X 2nd version development board equipped with an R-Car M3-W+ SiP with 8 (2 x 4) GiB of RAM. The memory map is as follows: - Bank0: 4GiB RAM : 0x000048000000 -> 0x000bfffffff 0x000480000000 -> 0x004ffffffff - Bank1: 4GiB RAM : 0x000600000000 -> 0x006ffffffff Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023123342.13100-10-geert+renesas@glider.be
| | * | | | | | | | | | | | arm64: dts: renesas: Add Renesas R8A77961 SoC supportGeert Uytterhoeven2019-11-011-0/+723
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for the Renesas R-Car M3-W+ (R8A77961) SoC. This includes: - Cortex-A57 and Cortex-A53 CPU cores (incl. L2 caches and power state definitions), - Power Management Unit, - PSCI firmware, - Pin Function Controller, - Clock, Reset, System, and Interrupt Controllers, - SCIF2 serial console, - Product Register, - ARM Architectured Timer, and various placeholders to allow to use salvator-xs.dtsi. Based on r8a7796.dtsi. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023123342.13100-9-geert+renesas@glider.be
| | * | | | | | | | | | | | arm64: dts: renesas: Prepare for rename of ARCH_R8A7796 to ARCH_R8A77960Geert Uytterhoeven2019-11-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_ARCH_R8A7796 for R-Car M3-W (R8A77960) will be renamed to CONFIG_ARCH_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_ARCH_R8A77961. Relax dependencies by handling both symbols. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023123342.13100-8-geert+renesas@glider.be
| | * | | | | | | | | | | | arm64: dts: renesas: r8a774b1: Add SATA controller nodeFabrizio Castro2019-10-251-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the SATA controller node to the RZ/G2N SoC specific dtsi. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Link: https://lore.kernel.org/r/1571761279-17347-3-git-send-email-fabrizio.castro@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | | | | | | | | | | | arm64: dts: renesas: rcar-gen3: Add CMM unitsJacopo Mondi2019-10-215-2/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CMM units to Renesas R-Car Gen3 SoC that support it, and reference them from the Display Unit they are connected to. Sort the 'vsps', 'renesas,cmm' and 'status' properties in the DU unit consistently in all the involved DTS. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20191016085548.105703-8-jacopo+renesas@jmondi.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | | | | | | | | | | | arm64: dts: renesas: r8a774b1: Add VIN and CSI-2 supportBiju Das2019-10-211-0/+366
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add VIN and CSI-2 support to the RZ/G2N SoC specific dtsi. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1571137271-33973-1-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | | | | | | | | | | | Merge tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi ↵Olof Johansson2019-11-031-0/+38
| |\ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into arm/dt ARM64: DT: Hisilicon SoCs DT updates for 5.5 - add Mali450 MP4 GPU node in the hi6220 SoC * tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi: arm64: dts: hisilicon: Add Mali-450 MP4 GPU DT entry Link: https://lore.kernel.org/r/5DB95AAB.8060405@hisilicon.com Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | | | | | | arm64: dts: hisilicon: Add Mali-450 MP4 GPU DT entryPeter Griffin2019-10-261-0/+38
| | | |/ / / / / / / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hi6220 has a Mali450 MP4 so lets add it into the DT. Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | | | | | | | | | | | | Merge tag 'realtek-arm64-dt-for-5.5' of ↵Olof Johansson2019-11-038-6/+231
| |\ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into arm/dt Realtek ARM64 based SoC DT for v5.5 Add RTD1293 and RTD1296 DTs. Add the watchdog for all of RTD129x DTs. Add reset controllers for RTD129x and start using them for UARTs. * tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek: arm64: dts: realtek: Add RTD129x UART resets arm64: dts: realtek: Add RTD129x reset controller nodes dt-bindings: reset: Add Realtek RTD1295 arm64: dts: realtek: Add watchdog node for RTD129x arm64: dts: realtek: Add oscillator for RTD129x arm64: dts: realtek: Add RTD1296 and Synology DS418 dt-bindings: arm: realtek: Document RTD1296 and Synology DS418 arm64: dts: realtek: Add RTD1293 and Synology DS418j arm64: dts: realtek: Change dual-license from MIT to BSD dt-bindings: arm: realtek: Document RTD1293 and Synology DS418j dt-bindings: arm: realtek: Tidy up conversion to json-schema Link: https://lore.kernel.org/r/20191030041000.31848-2-afaerber@suse.de Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | | | | | | arm64: dts: realtek: Add RTD129x UART resetsAndreas Färber2019-10-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Associate the UART nodes with the corresponding reset controller bits. Signed-off-by: Andreas Färber <afaerber@suse.de>