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* davinci: defconfig update: add EMACKevin Hilman2009-05-281-3/+7
| | | | | | DaVinci EMAC driver is now upstream. Enable it in default defconfig. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: add SRAM allocatorDavid Brownell2009-05-284-1/+103
| | | | | | | | | | | | | | | | | | | Provide a generic SRAM allocator using genalloc, and vaguely modeled after what AVR32 uses. This builds on top of the static CPU mapping set up in the previous patch, and returns DMA mappings as requested (if possible). Compared to its OMAP cousin, there's no current support for (currently non-existent) DaVinci power management code running in SRAM; and this has ways to deallocate, instead of being allocate-only. The initial user of this should probably be the audio code, because EDMA from DDR is subject to various dropouts on at least DM355 and DM6446 chips. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: soc-specific SRAM setupDavid Brownell2009-05-284-0/+33
| | | | | | | | | | | | | | | | | Package on-chip SRAM. It's always accessible from the ARM, so set up a standardized virtual address mapping into a 128 KiB area that's reserved for platform use. In some cases (dm6467) the physical addresses used for EDMA are not the same as the ones used by the ARM ... so record that info separately in the SOC data, for chips (unlike the OMAP-L137) where SRAM may be used with EDMA. Other blocks of SRAM, such as the ETB buffer or DSP L1/L2 RAM, may be unused/available on some system. They are ignored here. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: remove remnants of IRAM allocatorDavid Brownell2009-05-282-5/+0
| | | | | | | | Remove remnants of dm6446-specific SRAM allocator, as preparation for a more generic replacement. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: cleanup: move dm355 UART2 define to dm355.cKevin Hilman2009-05-282-2/+2
| | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Move PINMUX defines to SoC filesMark A. Greer2009-05-285-11/+15
| | | | | | | | | | Different SoC have different numbers of pinmux registers and other resources that overlap with each other. To clean up the code and eliminate defines that overlap with each other, move the PINMUX defines to the SoC specific files. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Add compare register support to timer codeMark A. Greer2009-05-282-38/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Timer64p timer has 8 compare registers that can be used to generate interrupts when the timer value matches the compare reg's value. They do not disturb the timer itself. This can be useful when there is only one timer available for both clock events and clocksource. When enabled, the clocksource remains a continuous 32-bit counter but the clock event will no longer support periodic interrupts. Instead only oneshot timers will be supported and implemented by setting the compare register to the current timer value plus the period that the clock event subsystem is requesting. Compare registers support is enabled automatically when the following conditions are met: 1) The same timer is being used for clock events and clocksource. 2) The timer is the bottom half (32 bits) of the 64-bit timer (hardware limitation). 3) The the compare register offset and irq are not zero. Since the timer is always running, there is a hardware race in timer32_config() between reading the current timer value, and adding the period to the current timer value and writing the compare register. Testing on a da830 evm board with the timer clocked at 24 MHz and the processor clocked at 300 MHz, showed the number of counter ticks to do this ranged from 20-53 (~1-2.2 usecs) but usually around 41 ticks. This includes some artifacts from collecting the information. So, the minimum period should be at least 5 usecs to be safe. There is also an non-critical lower limit that the period should be since there is no point in setting an event that is much shorter than the time it takes to set the event, and get & handle the timer interrupt for that event. There can also be all sorts of delays from activities occuring elsewhere in the system (including hardware activitis like cache & TLB management). These are virtually impossible to quantify so a minimum period of 50 usecs was chosen. That will certianly be enough to avoid the actual hardware race but hopefully not large enough to cause unreasonably course-grained timers. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Integrate cp_intc support into low-level irq codeMark A. Greer2009-05-285-2/+32
| | | | | | | | | | Integrate the Common Platform Interrupt Controller (cp_intc) support into the low-level irq handling for davinci and similar platforms. Do it such that support for cp_intc and the original aintc can coexist in the same kernel binary. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Factor out emac mac address handlingMark A. Greer2009-05-285-65/+20
| | | | | | | | Factor out the code to extract that mac address from i2c eeprom. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Remove unused i2c eeprom_read/write routinesMark A. Greer2009-05-282-36/+0
| | | | | | | | The dm644x and dm646x board files have i2c eeprom read and write routines but they are not used so remove them. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Move emac platform_data to SoC-specific filesMark A. Greer2009-05-289-67/+46
| | | | | | | | | | | Since most of the emac platform_data is really SoC specific and not board specific, move it to the SoC-specific files. Put a pointer to the platform_data in the soc_info structure so the board-specific code can set some of the platform_data if it needs to. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Move serial platform_device into SoC-specific filesMark A. Greer2009-05-286-65/+135
| | | | | | | | | | | | | | | | | | | Currently, there is one set of platform_device and platform_data structures for all DaVinci SoCs. The differences in the data between the various SoCs is handled by davinci_serial_init() by checking the SoC type. However, as new SoCs appear, this routine will become more & more cluttered. To clean up the routine and make it easier to add support for new SoCs, move the platform_device and platform_data structures into the SoC-specific code and use the SoC infrastructure to provide access to the data. In the process, fix a bug where the wrong irq is used for uart2 of the dm646x. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Make GPIO code more genericMark A. Greer2009-05-286-31/+37
| | | | | | | | | | | | | | | | | | The current gpio code needs to know the number of gpio irqs there are and what the bank irq number is. To determine those values, it checks the SoC type. It also assumes that the base address and the number of irqs the interrupt controller uses is fixed. To clean up the SoC checks and make it support different base addresses and interrupt controllers, have the SoC-specific code set those values in the soc_info structure and have the gpio code reference them there. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Add watchdog base address flexibilityMark A. Greer2009-05-267-5/+12
| | | | | | | | | | The watchdog code currently hardcodes the base address of the timer its using. To support new SoCs, make it support timers at any address. Use the soc_info structure to do this. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Add base address and timer flexibilityMark A. Greer2009-05-267-55/+181
| | | | | | | | | | | The davinci timer code currently hardcodes the timer register base addresses, the timer irq numbers, and the timers to use for clock events and clocksource. This won't work for some a new SoC so put those values into the soc_info structure and set them up in the SoC-specific files. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Move interrupt ctlr info to SoC infrastructureMark A. Greer2009-05-268-214/+229
| | | | | | | | | | | | | | | | | | Use the SoC infrastructure to hold the interrupt controller information (i.e., base address, default priorities, interrupt controller type, and the number of IRQs). The interrupt controller base, although initially put in the soc_info structure's intc_base field, is eventually put in the global 'davinci_intc_base' so the low-level interrupt code can access it without a dereference. These changes enable the SoC default irq priorities to be put in the SoC-specific files, and the interrupt controller to be at any base address. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Move pinmux setup info to SoC infrastructureMark A. Greer2009-05-266-26/+25
| | | | | | | | | The pinmux register base and setup can be different for different SoCs so move the pinmux reg base, pinmux table (and its size) to the SoC infrastructure. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Add support for multiple PSCsMark A. Greer2009-05-268-14/+57
| | | | | | | | | | | | | | The current code to support the DaVinci Power and Sleep Controller (PSC) assumes that there is only one controller. This assumption is no longer valid so expand the support to allow greater than one PSC. To accomplish this, put the base addresses for the PSCs in the SoC infrastructure so it can be referenced by the PSC code. This also requires adding an extra parameter to davinci_psc_config() to specify the PSC that is to be enabled/disabled. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Add clock init call to common init routineMark A. Greer2009-05-265-3/+13
| | | | | | | | All of the davinci SoCs need to call davinci_clk_init() so put the call in the common init routine. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Support JTAG ID register at any addressMark A. Greer2009-05-268-128/+97
| | | | | | | | | | | | | | | | | | | | | | | The Davinci cpu_is_davinci_*() macros use the SoC part number and variant retrieved from the JTAG ID register to determine the type of cpu that the kernel is running on. Currently, the code to read the JTAG ID register assumes that the register is always at the same base address. This isn't true on some newer SoCs. To solve this, have the SoC-specific code set the JTAG ID register base address in soc_info structure and add a 'cpu_id' member to it. 'cpu_id' will be used by the cpu_is_davinci_*() macros to match the cpu id. Also move the info used to identify the cpu type into the SoC-specific code to keep all SoC-specific code together. The common code will read the JTAG ID register, search through an array of davinci_id structures to identify the cpu type. Once identified, it will set the 'cpu_id' member of the soc_info structure to the proper value and the cpu_is_davinci_*() macros will now work. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Encapsulate SoC-specific data in a structureMark A. Greer2009-05-2613-47/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | Create a structure to encapsulate SoC-specific information. This will assist in generalizing code so it can be used by different SoCs that have similar hardware but with minor differences such as having a different base address. The idea is that the code for each SoC fills out a structure with the correct information. The board-specific code then calls the SoC init routine which in turn will call a common init routine that makes a copy of the structure, maps in I/O regions, etc. After initialization, code can get a pointer to the structure by calling davinci_get_soc_info(). Eventually, the common init routine will make a copy of all of the data pointed to by the structure so the original data can be made __init_data. That way the data for SoC's that aren't being used won't consume memory for the entire life of the kernel. The structure will be extended in subsequent patches but initially, it holds the map_desc structure for any I/O regions the SoC/board wants statically mapped. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: EMAC platform supportKevin Hilman2009-05-268-27/+161
| | | | | | | Add SoC and platform-specific data and init for DaVinci EMAC network driver. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: MMC platform supportKevin Hilman2009-05-265-0/+271
| | | | | | Add SoC and platform-specific data and init for MMC driver. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: update davinci_all_defconfig for dm355, dm6467Kevin Hilman2009-05-261-3/+12
| | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: DM646x: add base SoC and board supportKevin Hilman2009-05-265-0/+714
| | | | | | | | | | Add support for DM646x SoC (a.k.a DaVinci HD) and its Evalution Module (EVM.) Original support done by Sudhakar Rajashekhara. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: DM355: add base SoC and board supportKevin Hilman2009-05-267-1/+1123
| | | | | | | | | | | | | | In addition, add board support for the DM355 Evaluation Module (EVM) and the DM355 Leopard board. Original DM355 EVM support done by Sandeep Paulraj, with significant updates and improvements by David Brownell. DM355 Leopord support done by Koen Kooi. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Koen Kooi <koen@beagleboard.org> Cc: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: DM644x: add support for SFFSDR boardHugo Villeneuve2009-05-263-0/+188
| | | | | Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: add platform support for watchdog timerKevin Hilman2009-05-263-5/+42
| | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: INTC: add support for TI cp_intcSergei Shtylyov2009-05-264-0/+222
| | | | | | | | | | Add support for Texas Instuments Common Platform Interrupt Controller (cp_intc) used on DA830/OMAP-L137. Signed-off-by: Steve Chen <schen@mvista.com> Signed-off-by: Mark Greer <mgreer@mvista.com> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: support different UART bases for zImage uncompressMark A. Greer2009-05-261-2/+17
| | | | | | | | | | The davinci pre-kernel boot code assumes that all platforms use the same UART base address for the console. That assumption is not longer valid with some newer SoCs so determine the console UART base address from the machine number passed in from bootloader. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: interrupts: get_irqnr_and_base: save an instructionTroy Kisky2009-05-261-2/+1
| | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: use 32-bit accesses for low-level debug macrosChaithrika U S2009-05-261-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch defines debug macros for low-level debugging for Davinci based platforms Tested on : - DM644x DaVinci EVM - DM646X DaVinciHD EVM - DM355 EVM This patch attempts to solve the low-level debug issue in DM646x. The UART on DM646x SoC allows only 32-bit access. The existing debug-macro.S uses the macros from debug-8250.S file. This led to garbage serial out in the case of DM646x. The inclusion of debug-8250.S does not allow for run time fix for this issue. There are compile time errors due to multiple definitions of the macros. Also when building a single image for multiple DaVinci Platforms, the ifdefs cannot be relied upon. The solution below does not include the debug-8250.S file and defines the necessary macros. This solution was arrived at after observing that word access does not affect the low-level debug messages on DM644x/DM355. The other approach to this issue is to use the UART module information available in the peripheral registers to decide the access mechanism. But this will have to be done for every access of UART specifically for DM646x. Also this calls for a modification of the debug-8250.S file. Signed-off-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: fixups for banked GPIO interrupt handlingKevin Hilman2009-05-261-1/+3
| | | | | | | | | | | | This patch seems to get me much more reliable performance using the GPIO banked interrupts on dm355 for the dm9000 driver. Changes include: - init GPIO handling along with normal GPIO init - mask the level-sensitive bank IRQ during handling Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: gpio irq enable tweaksDavid Brownell2009-05-261-6/+14
| | | | | | | | | | | | | | | | | Fix two IRQ triggering bugs affecting GPIO IRQs: - Make sure enabling with IRQ_TYPE_NONE ("default, unspecified") isn't a NOP ... default to both edges, at least one must work. - As noted by Kevin Hilman, setting the irq trigger type for a banked gpio interrupt shouldn't enable irqs that are disabled. Since GPIO IRQs haven't been used much yet, it's not clear these bugs could have affected anything. The few current users don't seem to have been obviously suffering from these issues. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* [ARM] 5517/1: integrator: don't put clock lookups in __initdataRabin Vincent2009-05-181-1/+1
| | | | | | | | Remove the __initdata annotation for the clock lookups, since they will be needed when loading modules which use clk_get(). Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5518/1: versatile: don't put clock lookups in __initdataRabin Vincent2009-05-181-1/+1
| | | | | | | | Remove the __initdata annotation for the clock lookups, since they will be needed when loading modules which use clk_get(). Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] mach-l7200: fix spelling of SYS_CLOCK_OFFPavel Roskin2009-05-181-1/+1
| | | | | | Signed-off-by: Pavel Roskin <proski@gnu.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Double check memmap is actually valid with a memmap has unexpected ↵Mel Gorman2009-05-181-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | holes V2 pfn_valid() is meant to be able to tell if a given PFN has valid memmap associated with it or not. In FLATMEM, it is expected that holes always have valid memmap as long as there is valid PFNs either side of the hole. In SPARSEMEM, it is assumed that a valid section has a memmap for the entire section. However, ARM and maybe other embedded architectures in the future free memmap backing holes to save memory on the assumption the memmap is never used. The page_zone linkages are then broken even though pfn_valid() returns true. A walker of the full memmap must then do this additional check to ensure the memmap they are looking at is sane by making sure the zone and PFN linkages are still valid. This is expensive, but walkers of the full memmap are extremely rare. This was caught before for FLATMEM and hacked around but it hits again for SPARSEMEM because the page_zone linkages can look ok where the PFN linkages are totally screwed. This looks like a hatchet job but the reality is that any clean solution would end up consumning all the memory saved by punching these unexpected holes in the memmap. For example, we tried marking the memmap within the section invalid but the section size exceeds the size of the hole in most cases so pfn_valid() starts returning false where valid memmap exists. Shrinking the size of the section would increase memory consumption offsetting the gains. This patch identifies when an architecture is punching unexpected holes in the memmap that the memory model cannot automatically detect and sets ARCH_HAS_HOLES_MEMORYMODEL. At the moment, this is restricted to EP93xx which is the model sub-architecture this has been reported on but may expand later. When set, walkers of the full memmap must call memmap_valid_within() for each PFN and passing in what it expects the page and zone to be for that PFN. If it finds the linkages to be broken, it assumes the memmap is invalid for that PFN. Signed-off-by: Mel Gorman <mel@csn.ul.ie> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'smp-fix'Russell King2009-05-178-72/+32
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| * [ARM] realview: fix broadcast tick supportRussell King2009-05-173-14/+6
| | | | | | | | | | | | | | | | | | | | Having discussed broadcast tick support with Thomas Glexiner, the broadcast tick devices should be registered with a higher rating than the global tick device, and it should have the ONESHOT and PERIODIC feature flags set. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Thomas Glexiner <tglx@linutronix.de>
| * [ARM] realview: remove useless smp_cross_call_done()Russell King2009-05-172-14/+0
| | | | | | | | | | | | | | | | smp_cross_call_done() is a no-op for MPCore, and since it's only used by platform code, there's no point in having it unless it's doing something. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] smp: fix cpumask usage in ARM SMP codeRussell King2009-05-176-46/+28
| | | | | | | | | | | | | | The ARM SMP code wasn't properly updated for the cpumask changes, which results in smp_timer_broadcast() broadcasting ticks to non-online CPUs. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 5513/1: Eurotech VIPER SBC: fix compilation errorRicardo Martins2009-05-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Compilation for this board yields the following errors: arch/arm/mach-pxa/viper.c:511: error: 'FFUART' undeclared here (not in a function) arch/arm/mach-pxa/viper.c:520: error: 'BTUART' undeclared here (not in a function) arch/arm/mach-pxa/viper.c:529: error: 'STUART' undeclared here (not in a function) Fix them by including the necessary header. Signed-off-by: Ricardo Martins <rasm@fe.up.pt> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 5509/1: ep93xx: clkdev enable UARTSHartley Sweeten2009-05-162-9/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the clkdev API support for the ep93xx uart clocks. The uarts available in the ep93xx have individual clock controls. The current implementation assumes that the bootloader has enabled the clocks before the kernel has booted. It also assumes that the bootloader has set the UARTBAUD bit indicating that the uarts are running off the 14.7456MHz external crystal. This fixes both issues. It also allows the uart clocks to be stopped when there are no users. Tested-by: Matthias Kaehlcke <matthias@kaehlcke.net> Cc: Ryan Mallon <ryan@bluewatersys.com> Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'omap-fixes' of ↵Russell King2009-05-168-24/+27
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
| * | ARM: OMAP2/3: Change omapfb to use clkdev for dispc and rfbi, v2Tony Lindgren2009-05-162-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes the framebuffer work on omap3. Also fix the clk_get usage for checkpatch.pl "ERROR: do not use assignment in if condition". Cc: Imre Deak <imre.deak@nokia.com> Cc: linux-fbdev-devel@lists.sourceforge.net Acked-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | ARM: OMAP3: Fix HW SAVEANDRESTORE shift defineKalle Jokiniemi2009-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP3430ES2_SAVEANDRESTORE_SHIFT macro is used by powerdomain code in "1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT" manner, but the definition was also (1 << 4), meaning we actually modified bit 16. So the definition needs to be 4. This fixes also a cold reset HW bug in OMAP3430 ES3.x where some of the efuse bits are not isolated during wake-up from off mode. This can cause randomish cold resets with off mode. Enabling the USBTLL hardware SAVEANDRESTORE causes the core power up assert to be delayed in a way that we will not get faulty values when boot ROM is reading the unisolated registers. Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | ARM: OMAP3: Fix number of GPIO lines for 34xxVikram Pandita2009-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | As per 3430 TRM, there are 6 banks [0 to 191] Signed-off-by: Tom Rix <Tom.Rix@windriver.com> Signed-off-by: Vikram Pandita <vikram.pandita@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | ARM: OMAP2/3: Add name for musb clocksTony Lindgren2009-05-122-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the clkdev, musb_core.c needs to register clock with name "ick". Once all the platforms using the musb driver have been converted to use clockdev, the clock name does not need to be passed from the low-level init code. Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | ARM: OMAP2: Fix SPI driver failure on 2420 when running multi-omap configJarkko Nikula2009-05-121-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | SPI driver will do unhandled fault on OMAP2420 if trying to probe non-existing SPI busses. Register those additional busses runtime only for cpus having them. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 05:16:44 +0000