linux.git - Linux kernel mainline tree

	Commit message (Collapse)	Author	Age	Files	Lines
*	blackfin: mem_init: update dmc config register	Bob Liu	2013-02-20	1	-1/+1
\| \| \| \| \| \|	Update dmc config register to increase memory performance. Signed-off-by: Bob Liu <lliubbo@gmail.com>
*	bfin: reorg clock init steps for bf609	Bob Liu	2012-07-24	1	-0/+212
\| \| \| \| \| \|	So that user can set the clocks through menuconfig. Signed-off-by: Bob Liu <lliubbo@gmail.com>
*	Blackfin: remove CONFIG_MEM_GENERIC_BOARD	Christian Dietrich	2010-08-06	1	-18/+0
\| \| \| \| \| \| \| \| \|	MEM_GENERIC_BOARD depends on GENERIC_BOARD, but this flag was removed in 4f25eb85d64640bc656e72917113a84701521b99, therefore all references to it from the source can be removed. Signed-off-by: Christian Dietrich <qy03fugy@stud.informatik.uni-erlangen.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
*	Blackfin: punt dead/unused flash mem_init settings	Mike Frysinger	2009-12-15	1	-153/+0
\| \| \| \| \| \| \| \|	I don't think these defines were ever used. At any rate, we have common bit defines for all parts as well as a Kconfig option to declare the EBIU async timings, and no one has really complained about this so far. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
*	Blackfin: bf526-ezbrd: handle different SDRAM chips	Graf Yang	2009-06-22	1	-0/+86
\| \| \| \| \| \| \| \|	The BF526-EZBRD changed SDRAM chips between board revisions, so create a timing table that can accommodate both. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
*	Blackfin: fix typo in TRAS define in mem_init.h header	Graf Yang	2009-06-22	1	-1/+1
\| \| \| \| \| \| \| \|	We defined SDRAM_tRAS to TRAS_4, but then wrongly defined SDRAM_tRAS_num to 3. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
*	Blackfin arch: Fix Bug - Kernel does not boot if re-program clocks	Michael Hennerich	2009-02-04	1	-1/+1
\| \| \| \| \| \| \| \| \| \|	On BF561 EBIU_SDGCTL bit 31 controls the SDRAM external data path width, typically set 0 for a 32-bit bus width. On other Blackfin derivatives this bit should be set by default. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
*	Blackfin arch: enable reprogram cclk and sclk for bf518f-ezbrd	Sonic Zhang	2009-01-07	1	-2/+4
\| \| \| \| \| \|	Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
*	Blackfin arch: fix bugs and unify BFIN_KERNEL_CLOCK option	Michael Hennerich	2009-01-07	1	-0/+362
	- remove duplicated code and headers - add option allowing arbitrary SDRAM/DDR Timing parameters. - mark automatically calculated timings as EXPERIMENTAL - fix comment header block Related to BUGs: - kernel boot up fails with CONFIG_BFIN_KERNEL_CLOCK item on. - kernel does not boot if re-program clocks [ Mike Frysinger <vapier.adi@gmail.com> - fix comment header - mark do_sync static - document the DMA shutdown - simplify SIC_IWR handling - fix ANOMALY_05000265 handling to work as intended ] Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>