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* [IA64-SGI] Add PROM feature set for device flush listPrarit Bhargava2006-01-261-18/+18
| | | | | | | Introduce PRF_DEVICE_FLUSH_LIST flag for older PROMs. Signed-off-by: Prarit Bhargava <prarit@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] XPC remove unnecessary GFP_DMA flagJes Sorensen2006-01-241-3/+3
| | | | | | | | Remove the GFP_DMA flag from XPC kmalloc() calls. Signed-off-by: Jes Sorensen <jes@sgi.com> Acked-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Scaling fix for simultaneous unaligned accessesJack Steiner2006-01-241-1/+2
| | | | | | | | Eliminate a hot shared cacheline that occurs if multiple cpus are taking unaligned exceptions. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] sn_dma_alloc_coherent should use gfp flagsTakashi Iwai2006-01-241-2/+2
| | | | | | | | | | | Takashi helped us track down a bad page state bug we thought was coming from alsa. It turns out we weren't paying attention to the gfp flags that were passed in to sn_dma_alloc_coherent(). From: Takashi Iwai <tiwai@suse.de> Signed-off-by: Greg Edwards <edwardsg@sgi.com> Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Jes Sorensen <jes@sgi.com>
* [IA64] Set the correct default OS status in the MCA handlerKeith Owens2006-01-241-1/+1
| | | | | | | | | sos->os_status is set to a default value of IA64_MCA_COLD_BOOT for an MCA, but then is incorrectly overwritten with IA64_MCA_SAME_CONTEXT (0). This makes SAL think that all MCAs have been recovered. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* Merge branch 'release' of ↵Linus Torvalds2006-01-1910-67/+123
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
| * [IA64] eliminate softlockup warningJohn Hawkes2006-01-191-0/+1
| | | | | | | | | | | | | | | | | | | | Fix an unnecessary softlockup watchdog warning in the ia64 uncached_build_memmap() that occurs occasionally at 256p and always at 512p. The problem occurs at boot time. Signed-off-by: John Hawkes <hawkes@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] sem2mutex: arch/ia64/kernel/perfmon.cJes Sorensen2006-01-191-5/+6
| | | | | | | | | | | | | | | | | | Migrate perfmon from using an old semaphore to a completion handler. Signed-off-by: Jes Sorensen <jes@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] sem2mutex: arch/ia64/ia32/sys_ia32.cJes Sorensen2006-01-191-16/+12
| | | | | | | | | | | | | | | | | | Migrate arch/ia64/ia32/sys_ia32 to using a mutex for mmap protection. Signed-off-by: Jes Sorensen <jes@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] sn2 mutex conversionJes Sorensen2006-01-174-39/+36
| | | | | | | | | | | | | | | | | | Migrate sn2 code to use mutex and completion events rather than semaphores. Signed-off-by: Jes Sorensen <jes@sgi.com> Acked-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] pass segment# on SN_SAL_IOIF_SLOT_{DIS,EN}ABLE callsMike Habeck2006-01-171-4/+8
| | | | | | | | | | | | | | | | Bugfix... the altix SN_SAL_IOIF_SLOT_ENABLE & SN_SAL_IOIF_SLOT_DISABLE SAL calls need to pass the segment# down Signed-off-by: Mike Habeck <habeck@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64-SGI] Older PROM WAR for device flush codePrarit Bhargava2006-01-172-3/+60
| | | | | | | | | | | | | | | | | | | | | | Work-around to temporarily support older PROMs with new flush device code. This code allows systems running older PROMs to continue to run on the new kernel base until a new official PROM is released. Signed-off-by: Prarit Bhargava <prarit@sgi.com> Acked-by: Jes Sorensen <jes@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [PATCH] e1000: Added disable packet split capabilityJesse Brandeburg2006-01-184-0/+4
|/ | | | | | | | | Adds the ability to disability packet split at compile time and use the legacy receive path on PCI express hardware. Made this a CONFIG option and modified the Kconfig, to reflect the new option. Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: John Ronciak <john.ronciak@intel.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
* Pull perfmon-montecito into release branchTony Luck2006-01-162-0/+271
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| * [IA64] Perfmon for MontecitoStephane Eranian2006-01-162-0/+271
| | | | | | | | | | | | | | Add Montecito PMU description table for perfmon2 Signed-off-by: Stephane Eranian <eranian@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64] Cleanup of arch/ia64/sn and include/asm-ia64/snPrarit Bhargava2006-01-1612-247/+257
| | | | | | | | | | | | | | | | Replace uintX_t declarations with uX declarations. Replace intX_t declarations with sX declarations. Signed-off-by: Prarit Bhargava <prarit@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64] Stop multiple pci_claim_resource() call for the same resourceKenji Kaneshige2006-01-161-5/+14
| | | | | | | | | | | | | | | | | | This patch fixes the bug that pci_claim_resource() is called multiple times for the same P2P bridge's resource structures if P2P bridges require their own PCI I/O resources. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64] Simple memory hot-add for ia64.Yasunori Goto2006-01-161-0/+36
|/ | | | | | | | | First step to memory hotplug for ia64 (add only, all new memory is added to node 0, does not use ZONE_EASY_RECLAIM yet). Signed-off-by: Yasunori Goto <y-goto@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [PATCH] Altix: ioc3 serial supportPatrick Gefre2006-01-142-0/+4
| | | | | | | | | | | | | | | Add driver support for a 2 port PCI IOC3-based serial card on Altix boxes: This is a re-submission. On the original submission I was asked to organize the code so that the MIPS ioc3 ethernet and serial parts could be used with this driver. Stanislaw Skowronek was kind enough to provide the shim layer for this - thanks Stanislaw. This patch includes the shim layer and the Altix PCI ioc3 serial driver. The MIPS merged ioc3 ethernet and serial support is forthcoming. Signed-off-by: Patrick Gefre <pfg@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/driver-2.6Linus Torvalds2006-01-141-8/+8
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| * [PATCH] Add tiocx bus_type probe/remove methodsRussell King2006-01-131-8/+8
| | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | [PATCH] remove unused tmp_buf_sem'sAdrian Bunk2006-01-141-1/+0
| | | | | | | | | | | | | | | | tmp_buf_sem sems to be a common name for something completely unused... Signed-off-by: Adrian Bunk <bunk@stusta.de> Acked-by: Greg Kroah-Hartman <gregkh@suse.de> ("usb portion") Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [IA64] build broken for ia64 simserial.cAndreas Schwab2006-01-131-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TTY layer buffering revamp broke ia64 in commit 33f0f88f1c51ae5c2d593d26960c760ea154c2e2 CC arch/ia64/hp/sim/simserial.o arch/ia64/hp/sim/simserial.c: In function `receive_chars': arch/ia64/hp/sim/simserial.c:170: error: structure has no member named `flip' ... and so on ... make[1]: *** [arch/ia64/hp/sim/simserial.o] Error 1 Patch from Andreas Schwab. Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64] prevent accidental modification of args in jprobe handlerZhang Yanmin2006-01-132-0/+84
| | | | | | | | | | | | | | | | | | | | | | When jprobe is hit, the function parameters of the original function should be saved before jprobe handler is executed, and restored it after jprobe handler is executed, because jprobe handler might change the register values due to tail call optimization by the gcc. Signed-off-by: Zhang Yanmin <yanmin.zhang@intel.com> Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64] Add hotplug cpu to salinfo.c, replace semaphore with mutexKeith Owens2006-01-131-51/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add hotplug cpu support to salinfo.c. The cpu_event field is a cpumask so use the cpu_* macros consistently, replacing the existing mixture of cpu_* and *_bit macros. Instead of counting the number of outstanding events in a semaphore and trying to track that count over user space context, interrupt context, non-maskable interrupt context and cpu hotplug, replace the semaphore with a test for "any bits set" combined with a mutex. Modify the locking to make the test for "work to do" an atomic operation. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64] Handle debug traps in fsys modeJason Uhlenkott2006-01-131-7/+19
| | | | | | | | | | | | | | | | We need to handle debug traps in fsys mode non-fatally. They can happen now that we have fsyscalls which contain probe instructions. Signed-off-by: Jason Uhlenkott <jasonuhl@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64-SGI] Fix sn_flush_device_kernel & spinlock initializationPrarit Bhargava2006-01-134-71/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch separates the sn_flush_device_list struct into kernel and common (both kernel and PROM accessible) structures. As it was, if the size of a spinlock_t changed (due to additional CONFIG options, etc.) the sal call which populated the sn_flush_device_list structs would erroneously write data (and cause memory corruption and/or a panic). This patch does the following: 1. Removes sn_flush_device_list and adds sn_flush_device_common and sn_flush_device_kernel. 2. Adds a new SAL call to populate a sn_flush_device_common struct per device, not per widget as previously done. 3. Correctly initializes each device's sn_flush_device_kernel spinlock_t struct (before it was only doing each widget's first device). Signed-off-by: Prarit Bhargava <prarit@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64] Hole in IA64 TLB flushing from system threadsJack Steiner2006-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I originally thought this was an bug only in the SN code, but I think I also see a hole in the generic IA64 tlb code. (Separate patch was sent for the SN problem). It looks like there is a bug in the TLB flushing code. During context switch, kernel threads (kswapd, for example) inherit the mm of the task that was previously running on the cpu. Normally, this is ok because the previous context is still loaded into the RR registers. However, if the owner of the mm migrates to another cpu, changes it's context number, and references a page before kswapd issues a tlb_purge for that same page, the purge will be done with a stale context number (& RR registers). Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64-SGI] Altix BTE error handling fixesRuss Anderson2006-01-132-14/+53
| | | | | | | | | | | | | | | | | | | | Altix (shub2) pushes the BTE clean-up into SAL. This patch correctly interfaces with the now implemented SAL call. It also fixes a bug when delaying clean-up to allow busy BTEs to complete (or error out). Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64] Fix conversion of pal_min_state physical addressFrancois Wellenrieter2006-01-131-1/+1
| | | | | | | | | | | | | | | | | | On return from INIT handler we must convert the address of the minstate area from a kernel virtual uncached address (0xC...) to physical uncached (0x8...). A typo (or thinko?) in the code converted to physical cached. Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64-SGI] move xpc.h to include/asm-ia64/sn (cleanup)Dean Nelson2006-01-133-6/+6
| | | | | | | | | | | | | | | | Cleanup a few items after moving xpc.h from arch/ia64/sn/kernel to include/asm-ia64/sn. Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64-SGI] move xpc.h to include/asm-ia64/snDean Nelson2006-01-131-1274/+0
| | | | | | | | | | | | | | Move xpc.h from arch/ia64/sn/kernel to include/asm-ia64/sn without change. Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64-SGI] move xpc_system_reboot()Dean Nelson2006-01-131-29/+29
| | | | | | | | | | | | | | | | Move xpc_system_reboot() to be closer to the file it calls for readability reasons (which are indeed subjective). Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64-SGI] ignoring loss of heartbeat while XPC is in kdebugDean Nelson2006-01-131-1/+27
| | | | | | | | | | | | | | | | Allow for the loss of heartbeat while in kdebug to be ignored by remote partitions. Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64-SGI] XPC and unregistering from notifier listsDean Nelson2006-01-131-4/+6
| | | | | | | | | | | | | | Only unregister from notifier lists if XPC is unloading. Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64-SGI] cleanup XPC disengage related messagesDean Nelson2006-01-133-23/+68
| | | | | | | | | | | | | | Cleanup the XPC disengage related messages that are printed to the log. Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64-SGI] ensure XPC disengage request is processedDean Nelson2006-01-134-11/+16
| | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem in XPC disengage processing whereby it was not seeing the request to disengage from a remote partition, so the disengage wasn't happening. The disengagement is suppose to transpire during the time a XPC channel is disconnecting, and should be completed before the channel is declared to be disconnected. Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | [IA64] Add stub entry to fsys.S for sys_migrate_pagesTony Luck2006-01-131-0/+1
|/ | | | | | | | | | | When this new syscall was added to ia64 in commit 39743889aaf76725152f16aa90ca3c45f6d52da3 fsys.S was forgotten. Add a ".data8 0" there to keep it in step. [Reported by Stephane Eranian] Signed-off-by: Tony Luck <tony.luck@intel.com>
* [PATCH] ia64: task_pt_regs()Al Viro2006-01-129-48/+47
| | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] ia64: task_thread_info()Al Viro2006-01-122-7/+7
| | | | | | | | | | on ia64 thread_info is at the constant offset from task_struct and stack is embedded into the same beast. Set __HAVE_THREAD_FUNCTIONS, made task_thread_info() just add a constant. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] scheduler cache-hot-autodetectakpm@osdl.org2006-01-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ) From: Ingo Molnar <mingo@elte.hu> This is the latest version of the scheduler cache-hot-auto-tune patch. The first problem was that detection time scaled with O(N^2), which is unacceptable on larger SMP and NUMA systems. To solve this: - I've added a 'domain distance' function, which is used to cache measurement results. Each distance is only measured once. This means that e.g. on NUMA distances of 0, 1 and 2 might be measured, on HT distances 0 and 1, and on SMP distance 0 is measured. The code walks the domain tree to determine the distance, so it automatically follows whatever hierarchy an architecture sets up. This cuts down on the boot time significantly and removes the O(N^2) limit. The only assumption is that migration costs can be expressed as a function of domain distance - this covers the overwhelming majority of existing systems, and is a good guess even for more assymetric systems. [ People hacking systems that have assymetries that break this assumption (e.g. different CPU speeds) should experiment a bit with the cpu_distance() function. Adding a ->migration_distance factor to the domain structure would be one possible solution - but lets first see the problem systems, if they exist at all. Lets not overdesign. ] Another problem was that only a single cache-size was used for measuring the cost of migration, and most architectures didnt set that variable up. Furthermore, a single cache-size does not fit NUMA hierarchies with L3 caches and does not fit HT setups, where different CPUs will often have different 'effective cache sizes'. To solve this problem: - Instead of relying on a single cache-size provided by the platform and sticking to it, the code now auto-detects the 'effective migration cost' between two measured CPUs, via iterating through a wide range of cachesizes. The code searches for the maximum migration cost, which occurs when the working set of the test-workload falls just below the 'effective cache size'. I.e. real-life optimized search is done for the maximum migration cost, between two real CPUs. This, amongst other things, has the positive effect hat if e.g. two CPUs share a L2/L3 cache, a different (and accurate) migration cost will be found than between two CPUs on the same system that dont share any caches. (The reliable measurement of migration costs is tricky - see the source for details.) Furthermore i've added various boot-time options to override/tune migration behavior. Firstly, there's a blanket override for autodetection: migration_cost=1000,2000,3000 will override the depth 0/1/2 values with 1msec/2msec/3msec values. Secondly, there's a global factor that can be used to increase (or decrease) the autodetected values: migration_factor=120 will increase the autodetected values by 20%. This option is useful to tune things in a workload-dependent way - e.g. if a workload is cache-insensitive then CPU utilization can be maximized by specifying migration_factor=0. I've tested the autodetection code quite extensively on x86, on 3 P3/Xeon/2MB, and the autodetected values look pretty good: Dual Celeron (128K L2 cache): --------------------- migration cost matrix (max_cache_size: 131072, cpu: 467 MHz): --------------------- [00] [01] [00]: - 1.7(1) [01]: 1.7(1) - --------------------- cacheflush times [2]: 0.0 (0) 1.7 (1784008) --------------------- Here the slow memory subsystem dominates system performance, and even though caches are small, the migration cost is 1.7 msecs. Dual HT P4 (512K L2 cache): --------------------- migration cost matrix (max_cache_size: 524288, cpu: 2379 MHz): --------------------- [00] [01] [02] [03] [00]: - 0.4(1) 0.0(0) 0.4(1) [01]: 0.4(1) - 0.4(1) 0.0(0) [02]: 0.0(0) 0.4(1) - 0.4(1) [03]: 0.4(1) 0.0(0) 0.4(1) - --------------------- cacheflush times [2]: 0.0 (33900) 0.4 (448514) --------------------- Here it can be seen that there is no migration cost between two HT siblings (CPU#0/2 and CPU#1/3 are separate physical CPUs). A fast memory system makes inter-physical-CPU migration pretty cheap: 0.4 msecs. 8-way P3/Xeon [2MB L2 cache]: --------------------- migration cost matrix (max_cache_size: 2097152, cpu: 700 MHz): --------------------- [00] [01] [02] [03] [04] [05] [06] [07] [00]: - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) [01]: 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) [02]: 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) [03]: 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) [04]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) [05]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) [06]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) [07]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - --------------------- cacheflush times [2]: 0.0 (0) 19.2 (19281756) --------------------- This one has huge caches and a relatively slow memory subsystem - so the migration cost is 19 msecs. Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Ken Chen <kenneth.w.chen@intel.com> Cc: <wilder@us.ibm.com> Signed-off-by: John Hawkes <hawkes@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] sched: add cacheflush() asmIngo Molnar2006-01-121-0/+10
| | | | | | | | | | Add per-arch sched_cacheflush() which is a write-back cacheflush used by the migration-cost calibration code at bootup time. Signed-off-by: Ingo Molnar <mingo@elte.hu> Cc: Nick Piggin <nickpiggin@yahoo.com.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] capable/capability.h (arch/)Randy Dunlap2006-01-115-0/+5
| | | | | | | | arch: Use <linux/capability.h> where capable() is used. Signed-off-by: Randy Dunlap <rdunlap@xenotime.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] kprobes: fix race in recovery of reentrant probeKeshavamurthy Anil S2006-01-111-0/+7
| | | | | | | | | | | | | | | | | There is a window where a probe gets removed right after the probe is hit on some different cpu. In this case probe handlers can't find a matching probe instance related to break address. In this case we need to read the original instruction at break address to see if that is not a break/int3 instruction and recover safely. Previous code had a bug where we were not checking for the above race in case of reentrant probes and the below patch fixes this race. Tested on IA64, Powerpc, x86_64. Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Merge ssh://master.kernel.org/pub/scm/linux/kernel/git/sam/kbuildLinus Torvalds2006-01-101-2/+1
|\ | | | | | | Fix up some trivial conflicts in {i386|ia64}/Makefile
| * kbuild: remove GCC_VERSIONSam Ravnborg2006-01-081-6/+1
| | | | | | | | | | | | | | | | | | | | | | This was causing some ordering problems. Remove the up-front evaluation and just revaluate the compiler version each time we need it. (The up-front evaluation was problematic because some architectures modify the value of $(CC)). Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
* | [PATCH] kprobes: arch_remove_kprobeAnil S Keshavamurthy2006-01-101-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently arch_remove_kprobes() is only implemented/required for x86_64 and powerpc. All other architecture like IA64, i386 and sparc64 implementes a dummy function which is being called from arch independent kprobes.c file. This patch removes the dummy functions and replaces it with #define arch_remove_kprobe(p, s) do { } while(0) Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] sanitize building of fs/compat_ioctl.cChristoph Hellwig2006-01-102-48/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that all these entries in the arch ioctl32.c files are gone [1], we can build fs/compat_ioctl.c as a normal object and kill tons of cruft. We need a special do_ioctl32_pointer handler for s390 so the compat_ptr call is done. This is not needed but harmless on all other architectures. Also remove some superflous includes in fs/compat_ioctl.c Tested on ppc64. [1] parisc still had it's PPP handler left, which is not fully correct for ppp and besides that ppp uses the generic SIOCPRIV ioctl so it'd kick in for all netdevice users. We can introduce a proper handler in one of the next patch series by adding a compat_ioctl method to struct net_device but for now let's just kill it - parisc doesn't compile in mainline anyway and I don't want this to block this patchset. Signed-off-by: Christoph Hellwig <hch@lst.de> Cc: Matthew Wilcox <willy@debian.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] common compat_sys_timer_createChristoph Hellwig2006-01-102-29/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The comment in compat.c is wrong, every architecture provides a get_compat_sigevent() for the IPC compat code already. This basically moves the x86_64 version to common code and removes all the others. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Paul Mackerras <paulus@samba.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: "David S. Miller" <davem@davemloft.net> Acked-by: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] /dev/mem: validate mmap requestsBjorn Helgaas2006-01-081-49/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a hook so architectures can validate /dev/mem mmap requests. This is analogous to validation we already perform in the read/write paths. The identity mapping scheme used on ia64 requires that each 16MB or 64MB granule be accessed with exactly one attribute (write-back or uncacheable). This avoids "attribute aliasing", which can cause a machine check. Sample problem scenario: - Machine supports VGA, so it has uncacheable (UC) MMIO at 640K-768K - efi_memmap_init() discards any write-back (WB) memory in the first granule - Application (e.g., "hwinfo") mmaps /dev/mem, offset 0 - hwinfo receives UC mapping (the default, since memmap says "no WB here") - Machine check abort (on chipsets that don't support UC access to WB memory, e.g., sx1000) In the scenario above, the only choices are - Use WB for hwinfo mmap. Can't do this because it causes attribute aliasing with the UC mapping for the VGA MMIO space. - Use UC for hwinfo mmap. Can't do this because the chipset may not support UC for that region. - Disallow the hwinfo mmap with -EINVAL. That's what this patch does. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Hugh Dickins <hugh@veritas.com> Cc: "Luck, Tony" <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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