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* MIPS: mscc: ocelot: enable FDMA usageAlexandre Belloni2022-07-051-4/+5
| | | | | | | | | Enable FDMA usage by adding "fdma" resource in regs and interrupts. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mscc: serval: rename pinctrl nodesMichael Walle2022-04-271-7/+7
| | | | | | | | The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mscc: ocelot: rename pinctrl nodesMichael Walle2022-04-272-5/+5
| | | | | | | | The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mscc: jaguar2: rename pinctrl nodesMichael Walle2022-04-273-13/+13
| | | | | | | | The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mscc: ocelot: mark the phy-mode for internal PHY portsVladimir Oltean2021-08-212-0/+8
| | | | | | | | | | | | | The ocelot driver was converted to phylink, and that expects a valid phy_interface_t. Without a phy-mode, of_get_phy_mode returns PHY_INTERFACE_MODE_NA, which is not ideal because phylink rejects that. The ocelot driver was patched to treat PHY_INTERFACE_MODE_NA as PHY_INTERFACE_MODE_INTERNAL to work with the broken DT blobs, but we should fix the device trees and specify the phy-mode too. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mscc: ocelot: disable all switch ports by defaultVladimir Oltean2021-08-213-0/+23
| | | | | | | | | | | | | | | | | | | The ocelot switch driver used to ignore ports which do not have a phy-handle property and not probe those, but this is not quite ok since it is valid to not have a phy-handle property if there is a fixed-link. It seems that checking for a phy-handle was a proxy for the proper check which is for the status, but that doesn't make a lot of sense, since the ocelot driver already iterates using for_each_available_child_of_node which skips the disabled ports, so I have no idea. Anyway, a widespread pattern in device trees is for a SoC dtsi to disable by default all hardware, and let board dts files enable what is used. So let's do that and enable only the ports with a phy-handle in the pcb120 and pcb123 device tree files. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mscc: Add serval supportGregory CLEMENT2020-11-125-1/+318
| | | | | | | | | | | Add a device trees and FIT image support for the Microsemi Serval SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mscc: Add jaguar2 supportGregory CLEMENT2020-11-126-0/+626
| | | | | | | | | | | Add a device trees and FIT image support for the Microsemi Jaguar2 SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mscc: Add luton PC0B91 device treeGregory CLEMENT2020-11-122-1/+34
| | | | | | | | | | Add a device tree for the Microsemi Luton PCB091 evaluation board. It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mscc: Add luton dtsiGregory CLEMENT2020-11-121-0/+116
| | | | | | | | | | | Add a device tree include file for the Microsemi Luton SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: mscc: Prepare configuration to handle more SoCsGregory CLEMENT2020-11-121-1/+1
| | | | | | | | | | | | | Ocelot belongs to a family of SoC named the VCore III. In order to add these new Soc, use the new symbol SOC_VCOREIII instead of a one dedicated to Ocelot. In order to avoid regression on driver building, the MSCC_OCELOT configuration symbol is kept until the driver will be converted. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* net: mscc: ocelot: add definitions for VCAP ES0 keys, actions and targetVladimir Oltean2020-09-291-1/+2
| | | | | | | | As a preparation step for the offloading to ES0, let's create the infrastructure for talking with this hardware block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: mscc: ocelot: add definitions for VCAP IS1 keys, actions and targetVladimir Oltean2020-09-291-1/+2
| | | | | | | | As a preparation step for the offloading to IS1, let's create the infrastructure for talking with this hardware block. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* MIPS: dts: ocelot: describe the load/save GPIOQuentin Schulz2020-06-241-1/+11
| | | | | | | | | | This patch adds a description of the load/save GPIN pin, used in the VSC8584 PHY for timestamping operations. The related pinctrl description is also added. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* MIPS: dts: mscc: Updated changed name for miim pinctrl functionLars Povlsen2020-05-141-1/+1
| | | | | | | | | | | | | | | | | | This is an add-on patch to the main SoC Sparx5 series (Message-ID: <20200513125532.24585-1-lars.povlsen@microchip.com>). This changes the miim pinctrl function name from "miim1" to "miim" due to refactoring in the driver, obsoleting the instance number. The change in the driver was to better fit new platforms, as the instance number is redundant information. Specifically, support for the Microchip Sparx5 SoC is being submitted, where this change became necessary. Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: dts: mscc: describe the PTP ready interruptAntoine Tenart2019-08-241-2/+2
| | | | | | | | | | | | | | | | | | This patch adds a description of the PTP ready interrupt, which can be triggered when a PTP timestamp is available on an hardware FIFO. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: davem@davemloft.net Cc: richardcochran@gmail.com Cc: alexandre.belloni@bootlin.com Cc: UNGLinuxDriver@microchip.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: netdev@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: thomas.petazzoni@bootlin.com Cc: allan.nielsen@microchip.com
* MIPS: dts: mscc: describe the PTP register rangeAntoine Tenart2019-08-241-1/+2
| | | | | | | | | | | | | | | | | | This patch adds one register range within the mscc,vsc7514-switch node, to describe the PTP registers. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: davem@davemloft.net Cc: richardcochran@gmail.com Cc: alexandre.belloni@bootlin.com Cc: UNGLinuxDriver@microchip.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: netdev@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: thomas.petazzoni@bootlin.com Cc: allan.nielsen@microchip.com
* net: mscc: ocelot: Add support for tcamHoratiu Vultur2019-06-021-2/+3
| | | | | | | | Add ACL support using the TCAM. Using ACL it is possible to create rules in hardware to filter/redirect frames. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
| | | | | | | | | | | | | | Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge tag 'mips_4.20' of ↵Linus Torvalds2018-10-264-1/+133
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Paul Burton: - kexec support for the generic MIPS platform when running on a CPU including the MIPS Coherence Manager & related hardware. - Improvements to the definition of memory barriers used around MMIO accesses, and fixes in their use. - Switch to CONFIG_NO_BOOTMEM from Mike Rapoport, finally dropping reliance on the old bootmem code. - A number of fixes & improvements for Loongson 3 systems. - DT & config updates for the Microsemi Ocelot platform. - Workaround to enable USB power on the Netgear WNDR3400v3. - Various cleanups & fixes. * tag 'mips_4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (51 commits) MIPS: Cleanup DSP ASE detection MIPS: dts: Change upper case to lower case MIPS: generic: Add Network, SPI and I2C to ocelot_defconfig MIPS: Loongson-3: Fix BRIDGE irq delivery problem MIPS: Loongson-3: Fix CPU UART irq delivery problem MIPS: Remove unused PREF, PREFE & PREFX macros MIPS: lib: Use kernel_pref & user_pref in memcpy() MIPS: Remove unused CAT macro MIPS: Add kernel_pref & user_pref helpers MIPS: Remove unused TTABLE macro MIPS: Remove unused PIC macros MIPS: Remove unused MOVN & MOVZ macros MIPS: Provide actually relaxed MMIO accessors MIPS: Enforce strong ordering for MMIO accessors MIPS: Correct `mmiowb' barrier for `wbflush' platforms MIPS: Define MMIO ordering barriers MIPS: mscc: add PCB120 to the ocelot fitImage MIPS: mscc: add DT for Ocelot PCB120 MIPS: memset: Limit excessive `noreorder' assembly mode use MIPS: memset: Fix CPU_DADDI_WORKAROUNDS `small_fixup' regression ...
| * MIPS: mscc: add DT for Ocelot PCB120Quentin Schulz2018-10-092-1/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Ocelot PCB120 evaluation board is different from the PCB123 in that it has 4 external VSC8584 (or VSC8574) PHYs. It uses the SoC's second MDIO bus for external PHYs which have a reversed address on the bus (i.e. PHY4 is on address 3, PHY5 is on address 2, PHY6 on 1 and PHY7 on 0). Here is how the PHYs are connected to the switch ports: port 0: phy0 (internal) port 1: phy1 (internal) port 2: phy2 (internal) port 3: phy3 (internal) port 4: phy7 port 5: phy4 port 6: phy6 port 9: phy5 Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20869/ Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: davem@davemloft.net Cc: andrew@lunn.ch Cc: f.fainelli@gmail.com Cc: allan.nielsen@microchip.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: netdev@vger.kernel.org Cc: thomas.petazzoni@bootlin.com Cc: antoine.tenart@bootlin.com
| * MIPS: dts: mscc: enable i2c on ocelot_pcb123Alexandre Belloni2018-09-051-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the i2c controller on ocelot PCB123. While there are no i2c devices on the board itself, it can be used to control the SFP transceivers. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20352/ Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com> Cc: James Hogan <jhogan@kernel.org> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: linux-i2c@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Allan Nielsen <allan.nielsen@microchip.com>
| * MIPS: dts: mscc: Add i2c on ocelotAlexandre Belloni2018-09-051-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ocelot has an i2c controller, add it. There is only one possible pinmux configuration so add it as well. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20353/ Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com> Cc: James Hogan <jhogan@kernel.org> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: linux-i2c@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Allan Nielsen <allan.nielsen@microchip.com>
* | MIPS: mscc: ocelot: add SerDes mux DT nodeQuentin Schulz2018-10-051-0/+5
| | | | | | | | | | | | | | | | | | | | | | The Microsemi Ocelot has a set of register for SerDes/switch port muxing as well as PCIe muxing for a specific SerDes, so let's add the device and all SerDes in the Device Tree. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Paul Burton <paul.burton@mips.com> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | MIPS: mscc: ocelot: make HSIO registers address range a sysconQuentin Schulz2018-10-051-5/+9
|/ | | | | | | | | | | HSIO contains registers for PLL5 configuration, SerDes/switch port muxing and a thermal sensor, hence we can't keep it in the switch DT node. Acked-by: Paul Burton <paul.burton@mips.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123Alexandre Belloni2018-07-311-0/+10
| | | | | | | | | | | | | | | | Ocelot PCB123 has a SPI NOR connected on its SPI bus. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20103/ Cc: Mark Brown <broonie@kernel.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-spi@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Allan Nielsen <allan.nielsen@microsemi.com>
* mips: dts: mscc: Add spi on OcelotAlexandre Belloni2018-07-311-0/+11
| | | | | | | | | | | | | | | | Add support for the SPI controller Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20101/ Cc: Mark Brown <broonie@kernel.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-spi@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Allan Nielsen <allan.nielsen@microsemi.com>
* MIPS: mscc: ocelot: add interrupt controller properties to GPIO controllerQuentin Schulz2018-07-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | The GPIO controller also serves as an interrupt controller for events on the GPIO it handles. An interrupt occurs whenever a GPIO line has changed. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20015/ Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: linux-gpio@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: thomas.petazzoni@bootlin.com
* MIPS: mscc: ocelot: add MIIM1 busQuentin Schulz2018-07-261-0/+16
| | | | | | | | | | | | | | | | | | | | | | There is an additional MIIM (MDIO) bus in this SoC so let's declare it in the dtsi. This bus requires GPIO 14 and 15 pins that need to be muxed. There is no support for internal PHY reset on this bus on the contrary of MIIM0 so there is only one register address space and not two. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20014/ Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: thomas.petazzoni@bootlin.com
* MIPS: mscc: ocelot: fix length of memory address space for MIIMQuentin Schulz2018-07-261-1/+1
| | | | | | | | | | | | | | | | | | | | | The length of memory address space for MIIM0 is from 0x7107009c to 0x710700bf included which is 36 bytes long in decimal, or 0x24 bytes in hexadecimal and not 0x36. Fixes: 49b031690abe ("MIPS: mscc: Add switch to ocelot") Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20013/ Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: thomas.petazzoni@bootlin.com
* mips: mscc: build FIT image for OcelotAlexandre Belloni2018-07-241-1/+1
| | | | | | | | | | | | | Ocelot now has a u-boot port, allow building FIT images instead of relying on the legacy detection and builtin DTB. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: James Hogan <jhogan@kernel.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19632/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
* MIPS: mscc: Connect phys to ports on ocelot_pcb123Alexandre Belloni2018-05-141-0/+20
| | | | | | | | | | | | Add phy to switch port connections for PCB123 for internal PHYs. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Cc: David S. Miller <davem@davemloft.net> Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Signed-off-by: James Hogan <jhogan@kernel.org>
* MIPS: mscc: Add switch to ocelotAlexandre Belloni2018-05-141-0/+88
| | | | | | | | | | | | Ocelot has an integrated switch, add support for it. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Cc: David S. Miller <davem@davemloft.net> Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Signed-off-by: James Hogan <jhogan@kernel.org>
* MIPS: dts: Avoid unneeded built-in.a in DTS dirsMasahiro Yamada2018-04-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | arch/mips/boot/dts/Makefile collects objects from sub-directories into built-in.a only when CONFIG_BUILTIN_DTB is enabled. Reflect it also to the sub-directory Makefiles. This suppresses unneeded built-in.a creation in arch/mips/boot/dts/*/ directories. While I am here, I replaced $(patsubst %.dtb, %.dtb.o, $(dtb-y)) with $(addsuffix .o, $(dtb-y)) to simplify the code a little bit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Mathieu Malaterre <malat@debian.org> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/19099/ Signed-off-by: James Hogan <jhogan@kernel.org>
* MIPS: mscc: Add ocelot PCB123 device treeAlexandre Belloni2018-03-212-0/+29
| | | | | | | | | | | | | Add a device tree for the Microsemi Ocelot PCB123 evaluation board. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Allan Nielsen <Allan.Nielsen@microsemi.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/18856/ Signed-off-by: James Hogan <jhogan@kernel.org>
* MIPS: mscc: Add ocelot dtsiAlexandre Belloni2018-03-212-0/+118
Add a device tree include file for the Microsemi Ocelot SoC. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Allan Nielsen <Allan.Nielsen@microsemi.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/18855/ Signed-off-by: James Hogan <jhogan@kernel.org>
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