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* Merge branch '4.0-fixes' into mips-for-linux-nextRalf Baechle2015-04-131-1/+35
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| * MIPS: Fix cpu_has_mips_r2_exec_hazard.Ralf Baechle2015-04-101-1/+32
| | | | | | | | | | | | | | | | | | | | Returns a non-zero value if the current processor implementation requires an IHB instruction to deal with an instruction hazard as per MIPS R2 architecture specification, zero otherwise. For a discussion, see http://patchwork.linux-mips.org/patch/9539/. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Add support for XPA.Steven J. Hill2015-03-191-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for extended physical addressing (XPA) so that 32-bit platforms can access equal to or greater than 40 bits of physical addresses. NOTE: 1) XPA and EVA are not the same and cannot be used simultaneously. 2) If you configure your kernel for XPA, the PTEs and all address sizes become 64-bit. 3) Your platform MUST have working HIGHMEM support. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Correct FP ISA requirementsMaciej W. Rozycki2015-04-081-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct ISA requirements for floating-point instructions: * the CU3 exception signifies a real COP3 instruction in MIPS I & II, * the BC1FL and BC1TL instructions are not supported in MIPS I, * the SQRT.fmt instructions are indeed supported in MIPS II, * the LDC1 and SDC1 instructions are indeed supported in MIPS32r1, * the CEIL.W.fmt, FLOOR.W.fmt, ROUND.W.fmt and TRUNC.W.fmt instructions are indeed supported in MIPS32, * the CVT.L.fmt and CVT.fmt.L instructions are indeed supported in MIPS32r2 and MIPS32r6, * the CEIL.L.fmt, FLOOR.L.fmt, ROUND.L.fmt and TRUNC.L.fmt instructions are indeed supported in MIPS32r2 and MIPS32r6, * the RSQRT.fmt and RECIP.fmt instructions are indeed supported in MIPS64r1, Also simplify conditionals for MIPS III and MIPS IV FPU instructions and the handling of the MOVCI minor opcode. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Correct `nofpu' non-functionalityMaciej W. Rozycki2015-04-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | The `cpu_has_fpu' feature flag must not be hardcoded to 1 or the `nofpu' kernel option will be ignored. Remove any such overrides and add a cautionary note. Hardcoding to 0 is fine for FPU-less platforms. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9694/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Add arch CDMM definitions and probingJames Hogan2015-03-311-0/+4
|/ | | | | | | | | | | | | | | | | | | Add architectural definitions and probing for the MIPS Common Device Memory Map (CDMM) region. When supported and enabled at a particular physical address, this region allows some number of per-CPU devices to be discovered and controlled via MMIO. A bit exists in Config3 to determine whether the feature is present, and a CDMMBase CP0 register allows the region to be enabled at a particular physical address. [ralf@linux-mips.org: Sort conflict with other patches.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9178/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as wellMarkos Chandras2015-02-171-1/+2
| | | | | | | MIPS R2 FPU instructions are also present in MIPS R6 so amend the preprocessor definitions to take MIPS R6 into consideration. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Add LLB bit and related feature for the Config 5 CP0 registerMarkos Chandras2015-02-171-0/+3
| | | | | | | | | | | | | | | | | | | The LLBIT (bit 4) in the Config5 CP0 register indicates the software availability of the Load-Linked bit. This bit is only set by hardware and it has the following meaning: 0: LLB functionality is not supported 1: LLB functionality is supported. The following feature are also supported: - ERETNC instruction. Similar to ERET but it does not clear the LLB bit in the LLAddr register. - CP0 LLAddr/LLB bit must be set - LLbit is software accessible through the LLAddr[0] This will be used later on to emulate R2 LL/SC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfoMarkos Chandras2015-02-171-0/+3
| | | | | | | Print 'mips64r6' and/or 'mips32r6' if the kernel is running on a MIPS R6 core. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: cpu: Add MIPSR6 ISA definitionsLeonid Yegoshin2015-02-171-4/+15
| | | | | | | Add MIPS R6 to the ISA definitions Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: detect presence of the FRE & UFR bitsPaul Burton2014-11-241-0/+4
| | | | | | | | | | | | | | Detect the presence of the Config5 FRE & UFE bits, as indicated by the FREP bit in FPIR. Record this as a CPU option bit, and provide a cpu_has_fre macro to ease checking of that option bit. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7678/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use WSBH/DSBH/DSHD on Loongson 3AChen Jie2014-09-221-0/+10
| | | | | | | | | Signed-off-by: chenj <chenj@lemote.com> Cc: linux-mips@linux-mips.org Cc: chenhc@lemote.com Patchwork: https://patchwork.linux-mips.org/patch/7542/ Patchwork: https://patchwork.linux-mips.org/patch/7550/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: detect presence of MAARsPaul Burton2014-08-021-0/+3
| | | | | | | | | | | Detect the presence of MAAR using the MRP bit in Config5, and record that presence using a CPU option bit. A cpu_has_maar macro will then allow code to conditionalise upon the presence of MAARs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7330/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add new option for unique RI/XI exceptionsLeonid Yegoshin2014-08-021-0/+3
| | | | | | | | | | | MIPSr5 added support for unique exception codes for the Read-Inhibit and Execute-Inhibit exceptions. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7338/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: cpu: Add new cpu option for Hardware Table Walker.Markos Chandras2014-08-021-0/+3
| | | | | | | | | | Moreover, report hardware page table walker support as 'htw' in the ASE list of /proc/cpuinfo, if the core implements this feature. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7334/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Don't use RI/XI with 32-bit kernels on 64-bit CPUsDavid Daney2014-05-301-1/+8
| | | | | | | | | | | | The TLB handlers cannot handle this case, so disable it for now. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7007/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Remove most ifdefery.Ralf Baechle2014-05-211-0/+11
| | | | | | | | Most of these tests should be runtime tests. This also finally means that on a MIPS III systems MIPS IV opcodes are going to result in an exception as they're supposed to. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: asm: cpu: Add cpu flag for Enhanced Virtual AddressingMarkos Chandras2014-03-261-1/+3
| | | | | | | The MIPS *Aptiv family uses bit 28 in Config5 CP0 register to indicate whether the core supports EVA or not. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Detect the MSA ASEPaul Burton2014-03-261-0/+6
| | | | | | | | | | | | | This patch adds support for probing the MSAP bit within the Config3 register in order to detect the presence of the MSA ASE. Presence of the ASE will be indicated in /proc/cpuinfo. The value of the MSA implementation register will be displayed at boot to aid debugging and verification of a correct setup, as is done for the FPU. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: features: Add initial support for Segmentation Control registersSteven J. Hill2014-01-221-0/+4
| | | | | | | | | | MIPS32R3 introduced a new set of Segmentation Control registers which increase the flexibility of the segmented-based memory scheme. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6131/
* MIPS: features: Add initial support for TLBINVF capable coresLeonid Yegoshin2014-01-221-0/+3
| | | | | | | | | | New Aptiv cores support the TLBINVF instruction for flushing the VTLB. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6130/
* MIPS: cpu-features.h: s/MIPS53/MIPS64/Maciej W. Rozycki2013-09-241-1/+1
| | | | | | | | | No support for MIPS53 processors yet. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5876/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Optimize current_cpu_type() for better code.Ralf Baechle2013-09-171-6/+0
| | | | | | | | | | | | | o Move current_cpu_type() to a separate header file o #ifdefing on supported CPU types lets modern GCC know that certain code in callers may be discarded ideally turning current_cpu_type() into a function returning a constant. o Use current_cpu_type() rather than direct access to struct cpuinfo_mips. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5833/
* MIPS: oprofile: Fix BUG due to smp_processor_id() in preemptible code.Ralf Baechle2013-08-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | current_cpu_type() is not preemption-safe. If CONFIG_PREEMPT is enabled then mipsxx_reg_setup() can be called from preemptible state. Added get_cpu()/put_cpu() pair to make it preemption-safe. This was found while testing oprofile with CONFIG_DEBUG_PREEMPT enable. /usr/zntestsuite # opcontrol --init /usr/zntestsuite # opcontrol --setup --event=L2_CACHE_ACCESSES:500 --event=L2_CACHE_MISSES:500 --no-vmlinux /usr/zntestsuite # opcontrol --start Using 2.6+ OProfile kernel interface. BUG: using smp_processor_id() in preemptible [00000000] code: oprofiled/1362 caller is mipsxx_reg_setup+0x11c/0x164 CPU: 0 PID: 1362 Comm: oprofiled Not tainted 3.10.4 #18 Stack : 00000006 70757465 00000000 00000000 00000000 00000000 80b173f6 00000037 80b10000 00000000 80b21614 88f5a220 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 89c49c00 89c49c2c 80721254 807b7927 8012c1d0 80b10000 80721254 00000000 00000552 88f5a220 80b1335c 807b78e6 89c49ba8 ... Call Trace: [<801099a4>] show_stack+0x64/0x7c [<80665520>] dump_stack+0x20/0x2c [<803a2250>] debug_smp_processor_id+0xe0/0xf0 [<8052df24>] mipsxx_reg_setup+0x11c/0x164 [<8052cd70>] op_mips_setup+0x24/0x4c [<80529cfc>] oprofile_setup+0x5c/0x12c [<8052b9f8>] event_buffer_open+0x78/0xf8 [<801c3150>] do_dentry_open.isra.15+0x2b8/0x3b0 [<801c3270>] finish_open+0x28/0x4c [<801d49b8>] do_last.isra.41+0x2cc/0xd00 [<801d54a0>] path_openat+0xb4/0x4c4 [<801d5c44>] do_filp_open+0x3c/0xac [<801c4744>] do_sys_open+0x110/0x1f4 [<8010f47c>] stack_done+0x20/0x44 Bug reported and original patch by Jerin Jacob <jerinjacobk@gmail.com>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Jerin Jacob <jerinjacobk@gmail.com>
* MIPS: Cleanup indentation and whitespaceTony Wu2013-07-011-16/+16
| | | | | | | Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5536/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPSDavid Daney2013-07-011-1/+5
| | | | | | | | | | | | | | | | | | | | | | As Jonas Gorske said in his patch: Disable cpu_has_mmips for everything but SEAD3 and MALTA. Most of these platforms are from before the micromips introduction, so they are very unlikely to implement it. Reduces an -Os compiled, uncompressed kernel image by 8KiB for BCM63XX. This patch taks a different approach than his, we gate the runtime test for microMIPS by the config symbol SYS_SUPPORTS_MICROMIPS. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5327/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Get rid of MIPS I flag and test macros.Ralf Baechle2013-07-011-1/+10
| | | | | | | | | | | | | | | | | | | | | | MIPS I is the ancestor of all MIPS ISA and architecture variants. Anything ever build in the MIPS empire is either MIPS I or at least contains MIPS I. If it's running Linux, that is. So there is little point in having cpu_has_mips_1 because it will always evaluate as true - though usually only at runtime. Thus there is no point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it. Little complication: traps.c was using a test for a pure MIPS I ISA as a test for an R3000-style cp0. To deal with that, use a check for cpu_has_3kex or cpu_has_4kex instead. cpu_has_3kex is a new macro. At the moment its default implementation is !cpu_has_4kex but this may eventually change if Linux is ever going to support the oddball MIPS processors R6000 and R8000 so users of either of these macros should not make any assumptions. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5551/
* MIPS: Build uasm-generated code only once to avoid CPU Hotplug problemHuacai Chen2013-05-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This and the next patch resolve memory corruption problems while CPU hotplug. Without these patches, memory corruption can triggered easily as below: On a quad-core MIPS platform, use "spawn" of UnixBench-5.1.3 (http:// code.google.com/p/byte-unixbench/) and a CPU hotplug script like this (hotplug.sh): while true; do echo 0 >/sys/devices/system/cpu/cpu1/online echo 0 >/sys/devices/system/cpu/cpu2/online echo 0 >/sys/devices/system/cpu/cpu3/online sleep 1 echo 1 >/sys/devices/system/cpu/cpu1/online echo 1 >/sys/devices/system/cpu/cpu2/online echo 1 >/sys/devices/system/cpu/cpu3/online sleep 1 done Run "hotplug.sh" and then run "spawn 10000", spawn will get segfault after a few minutes. This patch: Currently, clear_page()/copy_page() are generated by Micro-assembler dynamically. But they are unavailable until uasm_resolve_relocs() has finished because jump labels are illegal before that. Since these functions are shared by every CPU, we only call build_clear_page()/ build_copy_page() only once at boot time. Without this patch, programs will get random memory corruption (segmentation fault, bus error, etc.) while CPU Hotplug (e.g. one CPU is using clear_page() while another is generating it in cpu_cache_init()). For similar reasons we modify build_tlb_refill_handler()'s invocation. V2: 1, Rework the code to make CPU#0 can be online/offline. 2, Introduce cpu_has_local_ebase feature since some types of MIPS CPU need a per-CPU tlb_refill_handler(). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongbing Hu <huhb@lemote.com> Acked-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4994/ Acked-by: John Crispin <blogic@openwrt.org>
* Merge branch 'mips-next-3.9' of ↵Ralf Baechle2013-02-211-0/+7
|\ | | | | | | git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
| * MIPS: Probe for and report hardware virtualization support.David Daney2013-02-191-0/+4
| | | | | | | | | | | | | | | | | | | | The presence of the MIPS Virtualization Application-Specific Extension is indicated by CP0_Config3[23]. Probe for this and report it in /proc/cpuinfo. Signed-off-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4904/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * MIPS: Add support for the M14KEc core.Steven J. Hill2013-02-171-0/+3
| | | | | | | | | | | | Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4682/ Signed-off-by: John Crispin <blogic@openwrt.org>
* | MIPS: Add printing of ISA version in cpuinfo.Steven J. Hill2013-02-151-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Display the MIPS ISA version release in the /proc/cpuinfo file. [ralf@linux-mips.org: Add support for MIPS I ... IV legacy architecture revisions. Also differenciate between MIPS32 and MIPS64 versions instead of lumping them together as just r1 and r2. Note to application programmers: this indicates the CPU's ISA level It does not imply the current execution environment does support it. For example an O32 application seeing "mips64r2" would still be restricted by by the execution environment to 32-bit - but the kernel could run mips64r2 code. The same for a 32-bit kernel running on a 64-bit processor. This field doesn't include ASEs or optional architecture modules nor other detailed flags such as the availability of an FPU.] Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/4714/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-9/+9
|/ | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add detection of DSP ASE Revision 2.Steven J. Hill2012-10-111-0/+4
| | | | | | | | | | | [ralf@linux-mips.org: This patch really only detects the ASE and passes its existence on to userland via /proc/cpuinfo. The DSP ASE Rev 2. adds new resources but no resources that would need management by the kernel.] Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4165/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)Al Cooper2012-10-111-0/+4
| | | | | | | | | | | | | The PCI (Program Counter Interrupt) bit in the "cause" register is mandatory for MIPS32R2 cores, but has also been added to some R1 cores (BMIPS5000). This change adds a cpu feature bit to make it easier to check for and use this feature. Signed-off-by: Al Cooper <alcooperx@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/4106/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.Steven J. Hill2012-09-131-3/+0
| | | | | | | | Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files and use new 'cpu_has_rixi' instead. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: David Daney <david.daney@cavium.com>
* MIPS: Add base architecture support for RI and XI.Steven J. Hill2012-09-131-0/+3
| | | | | | | | | | | Originally both Read Inhibit (RI) and Execute Inhibit (XI) were supported by the TLB only for a SmartMIPS core. The MIPSr3(TM) Architecture now defines an optional feature to implement these TLB bits separately. Support for one or both features can be checked by looking at the Config3.RXI bit. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: David Daney <david.daney@cavium.com>
* MIPS: Update comment for cpu_has_clo_clzRalf Baechle2010-08-051-1/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Implement Read Inhibit/eXecute InhibitDavid Daney2010-02-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit (XI) bits in the page tables work. The upper two bits of EntryLo{0,1} are RI and XI when the feature is enabled in the PageGrain register. SmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to 64-bit systems by continuing to place the RI and XI bits in the top of EntryLo even when EntryLo is 64-bits wide. Because we need to carry the RI and XI bits in the PTE, the layout of the PTE is changed. There is a two instruction overhead in the TLB refill hot path to get the EntryLo bits into the proper position. Also the TLB load exception has to probe the TLB to check if RI or XI caused the exception. Also of note is that the layout of the PTE bits is done at compile and runtime rather than statically. In the 32-bit case this allows for the same number of PFN bits as before the patch as the _PAGE_HUGE is not supported in 32-bit kernels (we have _PAGE_NO_EXEC and _PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE). The patch is tested on Cavium Octeon+, but should also work on 32-bit systems with the Smart-MIPS ASE. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/952/ Patchwork: http://patchwork.linux-mips.org/patch/956/ Patchwork: http://patchwork.linux-mips.org/patch/962/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: 64-bit: Detect virtual memory sizeGuenter Roeck2010-02-021-0/+7
| | | | | | | | | | | | | | Linux kernel 2.6.32 and later allocate address space from the top of the kernel virtual memory address space. This patch implements virtual memory size detection for 64 bit MIPS CPUs to avoid resulting crashes. Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/935/ Reviewed-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC.David Daney2009-09-171-0/+3
| | | | | | | | | | | | | | | | | On some CPUs, it is more efficient to disable and enable interrupts in the kernel rather than use ll/sc for atomic operations. But if we were to set cpu_has_llsc to false, we would break the userspace futex interface (in asm/futex.h). We separate the two concepts, with a new predicate kernel_uses_llsc, that lets us disable the kernel's use of ll/sc while still allowing the futex code to use it. Also there were a couple of cases in bitops.h where we were using ll/sc unconditionally even if cpu_has_llsc were false. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.David Daney2009-06-171-0/+4
| | | | | | | | Some CPUs have implementation dependent rdhwr registers. Allow them to be enabled on a per CPU basis. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.David Daney2009-06-171-0/+4
| | | | | | | | | | Some CPUs do not need ehb instructions after writing CP0 registers. By allowing ehb generation to be overridden in cpu-feature-overrides.h, we can save a few instructions in the TLB handler hot paths. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enable CLO / CLZ instructions via separate CPU propertyRalf Baechle2009-05-141-0/+9
| | | | | | | This is useful for IDT RC32332, RC32334 and NEC VR5500 processors which do not implement the full MIPS32 / MIPS64 architecture. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Hook Cavium OCTEON cache init into cache.cDavid Daney2009-01-111-0/+3
| | | | | | | | | Follow precedent of other boards, and hook-up the CPU specific cache init. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: New feature test macro cpu_has_mips_rRalf Baechle2008-10-301-0/+2
| | | | | | | cpu_has_mips_r is true if a processor is MIPS32 or MIPS64, any architecture revision. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle2008-10-111-0/+219
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>