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* MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.David Daney2009-06-171-0/+4
| | | | | | | | Some CPUs have implementation dependent rdhwr registers. Allow them to be enabled on a per CPU basis. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.David Daney2009-06-171-0/+4
| | | | | | | | | | Some CPUs do not need ehb instructions after writing CP0 registers. By allowing ehb generation to be overridden in cpu-feature-overrides.h, we can save a few instructions in the TLB handler hot paths. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enable CLO / CLZ instructions via separate CPU propertyRalf Baechle2009-05-141-0/+9
| | | | | | | This is useful for IDT RC32332, RC32334 and NEC VR5500 processors which do not implement the full MIPS32 / MIPS64 architecture. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Hook Cavium OCTEON cache init into cache.cDavid Daney2009-01-111-0/+3
| | | | | | | | | Follow precedent of other boards, and hook-up the CPU specific cache init. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: New feature test macro cpu_has_mips_rRalf Baechle2008-10-301-0/+2
| | | | | | | cpu_has_mips_r is true if a processor is MIPS32 or MIPS64, any architecture revision. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle2008-10-111-0/+219
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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