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* [MIPS] SMTC: irq_{enter,leave} and kstats keeping for relayed timer ints.Ralf Baechle2007-03-291-0/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Make SMTC_IDLE_HOOK_DEBUG a proper option in Kconfig.debug.Ralf Baechle2007-02-261-11/+8
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Make a bunch of functions and variables static.Ralf Baechle2007-02-061-9/+9
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Whitespace cleanups.Ralf Baechle2007-02-061-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: remove unused atomic_postclearRalf Baechle2007-02-061-22/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Define MIPS_CPU_IRQ_BASE in generic headerAtsushi Nemoto2007-02-061-11/+1
| | | | | | | | | | | | | | | | | | | | | | The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Fix module build by exporting symbolRalf Baechle2007-01-241-0/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Fix TLB sizing bug for TLB of 64 >= entriesRalf Baechle2007-01-241-2/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Instant IPI replay.Ralf Baechle2007-01-231-21/+33
| | | | | | | | | | | | SMTC pseudo-interrupts between TCs are deferred and queued if the target TC is interrupt-inhibited (IXMT). In the first SMTC prototypes, these queued IPIs were serviced on return to user mode, or on entry into the kernel idle loop. The INSTANT_REPLAY option dispatches them as part of local_irq_restore() processing, which adds runtime overhead (hence the option to turn it off), but ensures that IPIs are handled promptly even under heavy I/O interrupt load. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Fix cp0 hazard.Ralf Baechle2007-01-191-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irqAtsushi Nemoto2006-11-301-0/+1
| | | | | | | | | | | | | | Further incorporation of generic irq framework. Replacing __do_IRQ() by proper flow handler would make the irq handling path a bit simpler and faster. * use generic_handle_irq() instead of __do_IRQ(). * use handle_level_irq for obvious level-type irq chips. * use handle_percpu_irq for irqs marked as IRQ_PER_CPU. * setup .eoi routine for irq chips possibly used with handle_percpu_irq. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Synchronize cp0 counters on bootup.Ralf Baechle2006-11-011-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Complete fixes after removal of pt_regs argument to int handlers.Ralf Baechle2006-10-081-13/+13
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Replace board_timer_setup function pointer by plat_timer_setup.Ralf Baechle2006-07-131-1/+1
| | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
* [MIPS] SMTC: Reformat to Linux style.Ralf Baechle2006-07-131-29/+29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [PATCH] irq-flags: MIPS: Use the new IRQF_ constantsThomas Gleixner2006-07-021-1/+1
| | | | | | | | | | | | Use the new IRQF_ constants and remove the SA_INTERRUPT define Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@elte.hu> Cc: "David S. Miller" <davem@davemloft.net> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] spin/rwlock init cleanupsIngo Molnar2006-06-271-2/+2
| | | | | | | | | | | | | | | | | | | | | locking init cleanups: - convert " = SPIN_LOCK_UNLOCKED" to spin_lock_init() or DEFINE_SPINLOCK() - convert rwlocks in a similar manner this patch was generated automatically. Motivation: - cleanliness - lockdep needs control of lock initialization, which the open-coded variants do not give - it's also useful for -rt and for lock debugging in general Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Arjan van de Ven <arjan@linux.intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [MIPS] MT: Improved multithreading support.Ralf Baechle2006-04-191-0/+1322
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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