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* MIPS: Change my email addressJohn Crispin2016-05-131-1/+1
| | | | | | | | | The old address is no longer valid. Use the my new one instead. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13201/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: Disable xbar fpi burst modeJohn Crispin2015-11-111-0/+41
| | | | | | | Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11458/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Fix check for return value of request_mem_region()Hauke Mehrtens2015-11-111-6/+6
| | | | | | | | | | | | request_mem_region() returns a pointer and not an integer with an error value. A check for "< 0" on a pointer will cause problems, replace it with not null checks instead. This was found with sparse. Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11395/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add misc clocksHauke Mehrtens2015-11-111-1/+3
| | | | | | | | Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11393/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add 1e103100.deu clockHauke Mehrtens2015-11-111-0/+6
| | | | | | | | Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11392/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add clock for mei driverHauke Mehrtens2015-11-111-0/+6
| | | | | | | | Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11391/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add pmu bits for ar10 and grx390Hauke Mehrtens2015-11-111-1/+56
| | | | | | | | Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11388/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add PMU bits for USB and SDIO devicesHauke Mehrtens2015-11-111-1/+23
| | | | | | | | | | This adds the PUM bits for USB and SDIO devices Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11387/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Deactivate most of the devices by defaultHauke Mehrtens2015-11-111-21/+28
| | | | | | | | | | | | | When the SoC starts up most of the devices should be deactivated by the PMU, they should be activated when they get used by their drivers. Some devices should not get deactivate at startup like the serial, register them in a special way. Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11386/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add support for setting PMU register on AR10 and GRX390Hauke Mehrtens2015-11-111-11/+73
| | | | | | | | | | This adds support for setting the PMU register on the AR10 and GRX390. Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11382/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add locking for PMU register and check status afterwardsHauke Mehrtens2015-11-111-5/+27
| | | | | | | | | | | | | | | | | The PMU register are accessed in a non atomic way and they could be accessed by different threads simultaneously, which could cause problems this patch adds locking around the PMU registers. In addition we now also wait till the PMU is actually deactivated. [ralf@linux-mips.org: Fix spelling mistake in commit message as noticed by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>.] Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11381/ Patchwork: https://patchwork.linux-mips.org/patch/11396/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* treewide: fix errors in printkMasanari Iida2014-09-011-1/+1
| | | | | | | | | This patch fix spelling typo in printk. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* MIPS: Panic messages should not end in \n.Ralf Baechle2013-10-291-1/+1
| | | | | | | Panic() is going to add a \n itself and it's annoying if a panic message rolls of the screen on a device with no scrollback. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: add GPHY clock gate bitsJohn Crispin2013-02-171-0/+1
| | | | | | | Explicitly enable the clock gate of the internal GPHYs found on xrx200. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4816/
* MIPS: lantiq: adds static clock for PP32John Crispin2013-02-171-5/+7
| | | | | | | | The Lantiq DSL SoCs have an internal networking processor. Add code to read the static clock rate. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4815/
* MIPS: lantiq: trivial typo fixJohn Crispin2013-02-171-1/+1
| | | | | | | "nodes" is written with a single "s" Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4814/
* MIPS: lantiq: adds xrx200 ethernet clock definitionJohn Crispin2012-11-111-0/+4
| | | | | Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4521
* Merge branch 'master' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle2012-10-051-0/+2
|\ | | | | | | mips-for-linux-next
| * MIPS: lantiq: explicitly enable clkout generationJohn Crispin2012-08-221-0/+2
| | | | | | | | | | | | | | | | Previously we relied on the bootloader to have enabled this bit. However some bootloaders seem to not enable this for us. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4120/
* | MIPS: lantiq: enable pci clk conditional for xrx200 SoCJohn Crispin2012-08-231-1/+2
|/ | | | | | | | The xrx200 SoC family has the same PCI clock register layout as the AR9. Enable the same quirk as for AR9 Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4235/
* MIPS: Lantiq: Fix interface clock and PCI control register offsetJohn Crispin2012-08-011-21/+28
| | | | | | | | | | | The XRX200 based SoC have a different register offset for the interface clock and PCI control registers. This patch detects the SoC and sets the register offset at runtime. This make PCI work on the VR9 SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4113/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: remove orphaned codeJohn Crispin2012-05-261-0/+4
| | | | | | | | | | Now that all drivers are converted to OF we are able to remove some remaining pieces of orphaned code. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3841/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: implement support for clkdev apiJohn Crispin2012-05-211-0/+367
This patch unifies all clock generation and gating code into one file. All drivers will now be able to request their clocks via their device. This patch also adds support for the clockout feature, which allows clock generation on external pins. Support for COMMON_CLK will be provided in the next series. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3804/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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