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path: root/arch/mips/mm/c-r4k.c
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* MIPS: Remove wait argument of r4k_on_each_cpuRalf Baechle2010-10-291-11/+9
* MIPS: More detailed description of r4k_on_each_cpuRalf Baechle2010-10-291-0/+1
* MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.Ralf Baechle2009-06-241-0/+1
* MIPS: Support 64-byte D-cache line sizeKevin Cernekee2009-06-171-0/+12
* MIPS: Print the actual detected I-cache associativity on bootup.Ralf Baechle2009-05-141-1/+1
* MIPS: Alchemy: unify CPU model constants.Manuel Lauss2009-03-301-12/+5
* MIPS: VR5500: Enable prefetchShinya Kuribayashi2009-03-231-1/+1
* MIPS: Avoid destructive invalidation on partial cachelines.Ralf Baechle2009-01-301-1/+21
* [MIPS] Fix WARNING: at kernel/smp.c:290Thomas Bogendoerfer2008-09-051-6/+12
* smp_call_function: get rid of the unused nonatomic/retry argumentJens Axboe2008-06-261-9/+9
* [MIPS] Fix buggy use of kmap_coherent.Ralf Baechle2008-06-161-2/+5
* [MIPS] Fix build for PNX platforms.Ralf Baechle2008-06-161-0/+26
* [MIPS] Add support for MIPS CMP platform.Ralf Baechle2008-04-281-6/+37
* [MIPS] Allow setting of the cache attribute at run time.Chris Dearman2008-04-281-1/+18
* [MIPS] Handle aliases in vmalloc correctly.Ralf Baechle2008-04-071-0/+14
* [MIPS] Fix loads of section missmatchesRalf Baechle2008-03-121-15/+15
* [MIPS] Handle I-cache coherency in flush_cache_range()Ralf Baechle2008-02-191-3/+6
* arch/mips/: Spelling fixesJoe Perches2008-02-031-1/+1
* [MIPS] Alchemy: Au1210/Au1250 CPU supportManuel Lauss2008-01-291-0/+2
* [MIPS] Use real cache invalidateThomas Bogendoerfer2008-01-291-2/+2
* [MIPS] Remove useless S-cache flushes.Ralf Baechle2008-01-291-9/+0
* [MIPS] Use pte_present instead of open coded test for _PAGE_PRESENT.Ralf Baechle2008-01-291-1/+1
* [MIPS] Sibyte: resurrect old cache hack.Ralf Baechle2007-11-151-1/+6
* [MIPS] MT: Fix bug in multithreaded kernels.Ralf Baechle2007-10-291-3/+18
* [MIPS] Cache: Provide more information on cache policy on bootup.Ralf Baechle2007-10-161-3/+7
* [MIPS] checkfiles: Fix "need space after that ','" errors.Ralf Baechle2007-10-111-4/+4
* [MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle2007-10-111-6/+6
* [MIPS] Avoid indexed cacheops.Ralf Baechle2007-10-111-46/+28
* [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle2007-10-111-4/+18
* [MIPS] Replace use of stext with _stext.Ralf Baechle2007-07-311-2/+2
* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-101-0/+54
* [MIPS] Avoid dupliate D-cache flush on R400C / R4400 SC and MC variants.Ralf Baechle2006-11-301-3/+7
* [MIPS] Remove redundant r4k_blast_icache() callsAtsushi Nemoto2006-11-301-8/+4
* [MIPS] Remove __flush_icache_pageAtsushi Nemoto2006-10-011-77/+0
* [MIPS] c-r4k: Convert init functions from inline to __init.Ralf Baechle2006-09-271-10/+10
* [MIPS] Do not use drop_mmu_context to flusing other task's VIPT I-cache.Atsushi Nemoto2006-09-271-2/+2
* [MIPS] Retire flush_icache_page from mm use.Ralf Baechle2006-09-271-1/+1
* [MIPS] c-r4k: Typo fix.Ralf Baechle2006-09-271-1/+1
* [MIPS] vr41xx: Replace magic number for P4K bit with symbol.Yoichi Yuasa2006-07-131-1/+1
* [MIPS] vr41xx: Changed workaround to recommended methodYoichi Yuasa2006-07-131-4/+3
* [MIPS] VR41xx: Set VR41_CONF_BP only for PrId 0x0c80.Yoichi Yuasa2006-07-131-1/+3
* [MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle2006-07-131-4/+4
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-301-1/+0
* [MIPS] 74K: Assume it will also have an AR bit in config7Ralf Baechle2006-06-291-0/+1
* [MIPS] Treat CPUs with AR bit as physically indexed.Ralf Baechle2006-06-291-3/+8
* [MIPS] Fix handling of 0 length I & D caches.Chris Dearman2006-06-291-23/+41
* [MIPS] MIPS32/MIPS64 secondary cache managementChris Dearman2006-06-291-5/+18
* [MIPS] Save write-only Config.OD from being clobberedSergei Shtylyov2006-06-061-0/+34
* [MIPS] Treat R14000 like R10000.Kumba2006-06-011-0/+4
* [MIPS] Fix deadlock on MP with cache aliases.Ralf Baechle2006-06-011-9/+30
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