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path: root/arch/mips/mm/sc-mips.c
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* MIPS: Add P6600 cases to CPU switch statementsPaul Burton2016-05-131-0/+1
* MIPS: scache: Fix scache init with invalid line size.Govindraj Raja2016-02-291-4/+9
* MIPS: Fix early CM probingPaul Burton2016-02-091-10/+0
* MIPS: Enable L2 prefetching for CM >= 2.5Paul Burton2015-10-261-1/+60
* MIPS: Remove invalid checkAndrzej Hajda2015-10-261-2/+2
* MIPS: Add platform callback before initializing the L2 cacheMarkos Chandras2015-08-261-0/+10
* MIPS: CM3: Add support for CM3 L2 cache.Paul Burton2015-08-261-0/+32
* MIPS: mm: scache: Add secondary cache support for MIPS R6 coresMarkos Chandras2015-02-171-1/+2
* MIPS: Add cases for CPU_QEMU_GENERICLeonid Yegoshin2015-02-161-0/+1
* MIPS: Add cases for CPU_P5600James Hogan2014-03-261-0/+1
* MIPS: Add 1074K CPU support explicitly.Steven J. Hill2014-03-061-0/+1
* MIPS: Add support for interAptiv coresLeonid Yegoshin2014-01-221-0/+1
* MIPS: Add support for the proAptiv coresLeonid Yegoshin2014-01-221-0/+1
* MIPS: Optimize current_cpu_type() for better code.Ralf Baechle2013-09-171-1/+2
* MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker2013-07-141-1/+1
* MIPS: Fix ISA level which causes secondary cache init bypassing and moreDeng-Cheng Zhu2013-04-051-4/+2
* Disintegrate asm/system.h for MIPSDavid Howells2012-03-281-1/+0
* MIPS: Fix build errors in sc-mips.cKevin Cernekee2010-12-171-0/+4
* MIPS: Honor L2 bypass bitKevin Cernekee2010-10-291-4/+30
* MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.Kevin Cernekee2009-09-301-0/+5
* [MIPS] Fix loads of section missmatchesRalf Baechle2008-03-121-2/+1
* [MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle2007-10-111-1/+1
* [MIPS] MIPS32/MIPS64 S-cache fix and cleanupAtsushi Nemoto2006-06-291-32/+3
* [MIPS] MIPS32/MIPS64 secondary cache managementChris Dearman2006-06-291-0/+141
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