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* MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.Ralf Baechle2013-10-291-82/+87
| | | | | | It was ugly. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXTJayachandran C2013-10-291-33/+57
| | | | | | | | | | | | | | | | | | | | | | | Allow usage of scratch register for current pgd even when MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set for 64r2 platforms to indicate availability of Xcontext for saving cpuid, thus freeing Context to be used for saving PGD. This option was also tied to using a scratch register for storing PGD. This commit will allow usage of scratch register to store the current pgd if one can be allocated for the platform, even when MIPS_PGD_C0_CONTEXT is not set. The cpuid will be kept in the CP0 Context register in this case. The code to store the current pgd for the TLB miss handler is now generated in all cases. When scratch register is available, the PGD is also stored in the scratch register. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/5906/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move definition of SMP processor id register to header fileJayachandran C2013-10-291-50/+6
| | | | | | | | | | The definition of the CP0 register used to save the smp processor id is repicated in many files, move them all to thread_info.h. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5708/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Optimize current_cpu_type() for better code.Ralf Baechle2013-09-171-0/+1
| | | | | | | | | | | | | o Move current_cpu_type() to a separate header file o #ifdefing on supported CPU types lets modern GCC know that certain code in callers may be discarded ideally turning current_cpu_type() into a function returning a constant. o Use current_cpu_type() rather than direct access to struct cpuinfo_mips. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5833/
* MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2.David Daney2013-08-261-0/+2
| | | | | | | | | OCTEON2 need the same code. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5637/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2013-07-191-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS fixes from Ralf Baechle: "MIPS fixes for 3.11. Half of then is for Netlogic the remainder touches things across arch/mips. Nothing really dramatic and by rc1 standards MIPS will be in fairly good shape with this applied. Tested by building all MIPS defconfigs of which with this pull request four platforms won't build. And yes, it boots also on my favorite test systems" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: kvm: Kconfig: Drop HAVE_KVM dependency from VIRTUALIZATION MIPS: Octeon: Fix DT pruning bug with pip ports MIPS: KVM: Mark KVM_GUEST (T&E KVM) as BROKEN_ON_SMP MIPS: tlbex: fix broken build in v3.11-rc1 MIPS: Netlogic: Add XLP PIC irqdomain MIPS: Netlogic: Fix USB block's coherent DMA mask MIPS: tlbex: Fix typo in r3000 tlb store handler MIPS: BMIPS: Fix thinko to release slave TP from reset MIPS: Delete dead invocation of exception_exit().
| * MIPS: tlbex: fix broken build in v3.11-rc1Aaro Koskinen2013-07-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6ba045f9fbdafb48da42aa8576ea7a3980443136 (MIPS: Move generated code to .text for microMIPS) deleted tlbmiss_handler_setup_pgd_array, but some references were not converted. Fix that to enable building a MIPS kernel. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: Jayachandran C. <jchandra@broadcom.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5589/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: tlbex: Fix typo in r3000 tlb store handlerTony Wu2013-07-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | commit 6ba045f (MIPS: Move generated code to .text for microMIPS) causes a panic at boot. The handler builder should test against handle_tlbs_end, not handle_tlbs. Signed-off-by: Tony Wu <tung7970@gmail.com> Acked-by: Jayachandran C. <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5600/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker2013-07-141-77/+67
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch '3.10-fixes' into mips-for-linux-nextRalf Baechle2013-07-121-14/+42
|\ | | | | | | | | This that should have been fixed but weren't, way to much, intrusive and late.
| * MIPS: tlbex: Fix size of area to be flushed.Ralf Baechle2013-06-271-1/+1
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Flush TLB handlers directly after writing themJonas Gorski2013-06-251-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When having enabled MIPS_PGD_C0_CONTEXT, trap_init() might call the generated tlbmiss_handler_setup_pgd before it was committed to memory, causing boot failures: trap_init() |- per_cpu_trap_init() | |- TLBMISS_HANDLER_SETUP() | |- tlbmiss_handler_setup_pgd() |- flush_tlb_handlers() To avoid this, move flush_tlb_handlers() into build_tlb_refill_handler() right after they were generated. We can do this as the cache handling is initialized just before creating the tlb handlers. This issue was introduced in 3d8bfdd0307223de678962f1c1907a7cec549136 ("MIPS: Use C0_KScratch (if present) to hold PGD pointer."). Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Jayachandran C <jchandra@broadcom.com> Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/5539/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Fix TLBR-use hazards for R2 cores in the TLB reload handlersRalf Baechle2013-06-211-0/+26
| | | | | | | | | | | | | | | | | | | | MIPS R2 documents state that an execution hazard barrier is needed after a TLBR before reading EntryLo. Original patch by Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5526/
* | MIPS: Fix typos and cleanup commentTony Wu2013-07-011-1/+1
| | | | | | | | | | | | | | Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5535/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Move generated code to .text for microMIPSJayachandran C2013-07-011-40/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare of a next patch which will call tlbmiss_handler_setup_pgd on microMIPS. MicroMIPS complains if the called code s not in the .text section. To fix this we generate code into space reserved in arch/mips/mm/tlb-funcs.S While there, move the rest of the generated functions (handle_tlbl, handle_tlbs, handle_tlbm) to the same file. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5542/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Fixup check for invalid scratch registerJayachandran C2013-06-131-5/+5
| | | | | | | | | | | | | | | | | | | | | | The invalid value for scratch register is -1, so update the checks of the form (scratch_reg > 0) to be (scratch_reg >= 0). This will fix the case in Netlogic XLP where the scratch_reg can be 0. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5444/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Allow platform specific scratch registersJayachandran C2013-06-131-15/+26
|/ | | | | | | | | | | | | | | XLR/XLP COP0 scratch is register 22, sel 0-7. Add a function c0_kscratch() which returns the scratch register for the platform, and use the return value while generating TLB handlers. Setup kscratch_mask to 0xf for XLR/XLP since the config4 register does not exist. This allows the kernel to allocate scratch registers 0-3 if needed. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5445/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove duplicate definition of check_for_high_segbits.David Daney2013-05-231-4/+0
| | | | | | | | | In C, one definition is sufficient. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5304/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Revert "MIPS: Allow ASID size to be determined at boot time."David Daney2013-05-161-49/+0
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d532f3d26716a39dfd4b88d687bd344fbe77e390. The original commit has several problems: 1) Doesn't work with 64-bit kernels. 2) Calls TLBMISS_HANDLER_SETUP() before the code is generated. 3) Calls TLBMISS_HANDLER_SETUP() twice in per_cpu_trap_init() when only one call is needed. [ralf@linux-mips.org: Also revert the bits of the ASID patch which were hidden in the KVM merge.] Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: "Steven J. Hill" <Steven.Hill@imgtec.com> Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/5242/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Revert "MIPS: microMIPS: Support dynamic ASID sizing."David Daney2013-05-161-32/+2
| | | | | | | | | | | | | | This reverts commit f6b06d9361a008afb93b97fb3683a6e92d69d0f4. The next revert depends on this one, so this has to go too. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: "Steven J. Hill" <Steven.Hill@imgtec.com> Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/5241/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'mti-next' of ↵Ralf Baechle2013-05-091-0/+100
|\ | | | | | | git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
| * MIPS: microMIPS: Add support for exception handling.Steven J. Hill2013-05-091-0/+21
| | | | | | | | | | | | | | | | | | All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
| * MIPS: microMIPS: Support dynamic ASID sizing.Steven J. Hill2013-05-081-2/+32
| | | | | | | | | | | | | | | | | | | | Changes for pure microMIPS cores to dynamically determine the ASID size at boot time. Includes bug fix https://patchwork.linux-mips.org/patch/5230/ Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Jonas Gorski <jogo@openwrt.org>
| * MIPS: Allow ASID size to be determined at boot time.Steven J. Hill2013-05-081-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Original patch by Ralf Baechle and removed by Harold Koerfgen with commit f67e4ffc79905482c3b9b8c8dd65197bac7eb508. This allows for more generic kernels since the size of the ASID and corresponding masks can be determined at run-time. This patch is also required for the new Aptiv cores and has been tested on Malta and Malta Aptiv platforms. [ralf@linux-mips.org: Added relevant part of fix https://patchwork.linux-mips.org/patch/5213/] Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge branch 'mips-next-3.10' of ↵Ralf Baechle2013-05-081-2/+8
|\ \ | | | | | | | | | git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
| * | MIPS: Build uasm-generated code only once to avoid CPU Hotplug problemHuacai Chen2013-05-081-2/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This and the next patch resolve memory corruption problems while CPU hotplug. Without these patches, memory corruption can triggered easily as below: On a quad-core MIPS platform, use "spawn" of UnixBench-5.1.3 (http:// code.google.com/p/byte-unixbench/) and a CPU hotplug script like this (hotplug.sh): while true; do echo 0 >/sys/devices/system/cpu/cpu1/online echo 0 >/sys/devices/system/cpu/cpu2/online echo 0 >/sys/devices/system/cpu/cpu3/online sleep 1 echo 1 >/sys/devices/system/cpu/cpu1/online echo 1 >/sys/devices/system/cpu/cpu2/online echo 1 >/sys/devices/system/cpu/cpu3/online sleep 1 done Run "hotplug.sh" and then run "spawn 10000", spawn will get segfault after a few minutes. This patch: Currently, clear_page()/copy_page() are generated by Micro-assembler dynamically. But they are unavailable until uasm_resolve_relocs() has finished because jump labels are illegal before that. Since these functions are shared by every CPU, we only call build_clear_page()/ build_copy_page() only once at boot time. Without this patch, programs will get random memory corruption (segmentation fault, bus error, etc.) while CPU Hotplug (e.g. one CPU is using clear_page() while another is generating it in cpu_cache_init()). For similar reasons we modify build_tlb_refill_handler()'s invocation. V2: 1, Rework the code to make CPU#0 can be online/offline. 2, Introduce cpu_has_local_ebase feature since some types of MIPS CPU need a per-CPU tlb_refill_handler(). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongbing Hu <huhb@lemote.com> Acked-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4994/ Acked-by: John Crispin <blogic@openwrt.org>
* / MIPS: Make declarations and definitions of tlbmiss_handler_setup_pgd match.Ralf Baechle2013-04-111-11/+11
|/ | | | | | | | | tlbmiss_handler_setup_pgd is run-time generated code and it was convenient to pretend the symbol was an array in the generator but a function for the users. LTO gcc won't tolerate this kind of lie anymore so solve the problem through a cast and function pointer instead. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'mips-next-3.9' of ↵Ralf Baechle2013-02-211-0/+1
|\ | | | | | | git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
| * MIPS: Add support for the M14KEc core.Steven J. Hill2013-02-171-0/+1
| | | | | | | | | | | | Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4682/ Signed-off-by: John Crispin <blogic@openwrt.org>
* | MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-16/+16
|/ | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores."Ralf Baechle2012-12-271-16/+0
| | | | | | This reverts commit ff401e52100dcdc85e572d1ad376d3307b3fe28e. This breaks on MIPS64 R2 cores such as Broadcom's.
* Merge branch 'mips-next' of http://dev.phrozen.org/githttp/mips-next into ↵Ralf Baechle2012-12-131-2/+6
|\ | | | | | | mips-for-linux-next
| * MIPS: tlbex: Fix section mismatchesKevin Cernekee2012-11-091-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new functions introduced in commit 02a5417751 (MIPS: tlbex: Deal with re-definition of label) should be marked __cpuinit, to eliminate a warning that can pop up when CONFIG_EXPORT_UASM is disabled: LD arch/mips/mm/built-in.o WARNING: arch/mips/mm/built-in.o(.text+0x2a4c): Section mismatch in reference from the function uasm_bgezl_hazard() to the function .cpuinit.text:uasm_il_bgezl() The function uasm_bgezl_hazard() references the function __cpuinit uasm_il_bgezl(). This is often because uasm_bgezl_hazard lacks a __cpuinit annotation or the annotation of uasm_il_bgezl is wrong. WARNING: arch/mips/mm/built-in.o(.text+0x2a68): Section mismatch in reference from the function uasm_bgezl_label() to the function .cpuinit.text:uasm_build_label() The function uasm_bgezl_label() references the function __cpuinit uasm_build_label(). This is often because uasm_bgezl_label lacks a __cpuinit annotation or the annotation of uasm_build_label is wrong. (This warning might not occur if the function was inlined.) Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4517 Signed-off-by: John Crispin <blogic@openwrt.org>
* | MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle2012-12-131-18/+0
| | | | | | | | | | | | | | Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Transparent Huge Pages supportRalf Baechle2012-12-121-1/+2
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Control huge tlb support via Kconfig symbol MIPS_HUGE_TLB_SUPPORTDavid Daney2012-12-121-13/+13
| | | | | | | | | | | | | | | | We need Huge TLBs for HUGETLB_PAGE, or the soon to follow TRANSPARENT_HUGEPAGE. collect this information under a single Kconfig symbol. Signed-off-by: David Daney <david.daney@cavium.com>
* | MIPS: tlbex: Better debug output.Ralf Baechle2012-11-261-13/+55
| | | | | | | | | | | | | | | | | | | | | | | | Pgtable bits are assigned dynamically depending on processor feature and statically based on kernel configuration. To make sense out of the disassembled TLB exception handlers a list of the actual assignments used for a particular configuration and hardware setup can be very useful. Output the actual TLB exception handlers in a format that simplifies their post processsing from dmesg output. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Remove R5000A.Ralf Baechle2012-11-261-2/+0
|/ | | | | | | From a software perspective R5000 and R5000A are the same thing which is why the symbol CPU_R5000A never got used, so finally delete it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: R5000: Fix TLB hazard handling.Ralf Baechle2012-10-161-15/+8
| | | | | | | | | | | | R5000 and the Nevada CPUs (RM5230, RM5231, RM5260, RM5261, RM5270 and RM5271) are basically the same CPU core and all are documented to require two instructions separating a write to c0_pagemask, c0_entryhi, c0_entrylo0, c0_entrylo1 or c0_index. So far we were only providing on cycle before / after a TLBR/TLBWI for R5000 but 3 cycles before and 1 cycles after for the Nevadas. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: tlbex: Deal with re-definition of labelRalf Baechle2012-10-161-7/+34
| | | | | | | | | | | | | | The microassembler used in tlbex.c does not notice if a label is redefined resulting in relocations against such labels silently missrelocated. The issues exists since commit add6eb04776db4189ea89f596cbcde31b899be9d [Synthesize TLB exception handlers at runtime.] in 2.6.10 and went unnoticed for so long because the relocations for the affected branches got computed to do something *almost* sensible. The issue affects R4000, R4400, QED/IDT RM5230, RM5231, RM5260, RM5261, RM5270 and RM5271 processors. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Optimize TLB refill for RI/XI configurations.David Daney2012-10-111-16/+7
| | | | | | | | | | We don't have to do a separate shift to eliminate the software bits, just rotate them into the fill and they will be ignored. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4294/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'ralf-3.7' of ↵Ralf Baechle2012-09-281-1/+29
|\ | | | | | | git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
| * MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.Steven J. Hill2012-09-131-0/+16
| | | | | | | | | | | | | | The EXT and INS instructions can be used to decrease code size and thus speed up TLB handlers on MIPS32R2 and MIPS64R2 cores. Signed-off-by: Steven J. Hill <sjhill@mips.com>
| * MIPS: Avoid pipeline stalls on some MIPS32R2 cores.Steven J. Hill2012-09-131-1/+13
| | | | | | | | | | | | | | | | | | | | The architecture specification says that an EHB instruction is needed to avoid a hazard when writing TLB entries. However, some cores do not have this hazard, and thus the EHB instruction causes a costly pipeline stall. Detect these cores and do not use the EHB instruction. Signed-off-by: Steven J. Hill <sjhill@mips.com>
* | MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.Steven J. Hill2012-09-131-7/+7
|/ | | | | | | | Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files and use new 'cpu_has_rixi' instead. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: David Daney <david.daney@cavium.com>
* MIPS: Add support for the M14Kc core.Steven J. Hill2012-07-061-0/+2
| | | | | | | | | [ralf@linux-mips.org: Fixed whitespace damage.] Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3773/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Disintegrate asm/system.h for MIPSDavid Howells2012-03-281-0/+1
| | | | | | | | Disintegrate asm/system.h for MIPS. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> cc: linux-mips@linux-mips.org
* MIPS: No branches in delay slots for huge pages in handle_tlblDavid Daney2011-09-211-1/+2
| | | | | | | | | | For the case PM_DEFAULT_MASK == 0, we were placing a branch in the delay slot of another branch. This leads to undefined behavior. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2775/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: tlbex: Fix build error in R3000 code.Ralf Baechle2011-09-211-2/+1
| | | | | | | | | | | | | Only some GCC versions such as gcc 4.2 notice that the variable wr in build_r3000_tlb_modify_handler is used uninitialized. When using one of those GCCs the build will fail due to -Werror. GCC 4.6 does not warn about the uninitialized use of wr. This issue was introduced by 7211f4d7a3dcbe57c5d396c334dca525315dceb2 [MIPS: Close races in TLB modify handlers.] Reported-by: Ganesan Ramalingam <ganesan18@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Close races in TLB modify handlers.David Daney2011-07-261-98/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Page table entries are made invalid by writing a zero into the the PTE slot in a page table. This creates a race condition with the TLB modify handlers when they are updating the PTE. CPU0 CPU1 Test for _PAGE_PRESENT . set to not _PAGE_PRESENT (zero) Set to _PAGE_VALID So now the page not present value (zero) is suddenly valid and user space programs have access to physical page zero. We close the race by putting the test for _PAGE_PRESENT and setting of _PAGE_VALID into an atomic LL/SC section. This requires more registers than just K0 and K1 in the handlers, so we need to save some registers to a save area and then restore them when we are done. The save area is an array of cacheline aligned structures that should not suffer cache line bouncing as they are CPU private. [ralf@linux-mips.org: Fix !defined(CONFIG_MIPS_PGD_C0_CONTEXT) build error.] Signed-off-by: David Daney <david.daney@cavium.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2577/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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