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* Disable MSI also when pcie-octeon.pcie_disable onYunQiang Su2019-01-101-1/+3
| | | | | | | | | | | | | | | Octeon has an boot-time option to disable pcie. Since MSI depends on PCI-E, we should also disable MSI also with this option is on in order to avoid inadvertently accessing PCIe registers. Signed-off-by: YunQiang Su <ysu@wavecomp.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: pburton@wavecomp.com Cc: linux-mips@vger.kernel.org Cc: aaro.koskinen@iki.fi Cc: stable@vger.kernel.org # v3.3+
* MIPS/PCI: Use for_pci_msi_entry() to access MSI device listJiang Liu2015-07-221-1/+1
| | | | | | | | | | | | | | | | | | | | Use accessor for_each_pci_msi_entry() to access MSI device list, so we could easily move msi_list from struct pci_dev into struct device later. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Stuart Yoder <stuart.yoder@freescale.com> Cc: Yijing Wang <wangyijing@huawei.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Ralf Baechle <ralf@linux-mips.org> Link: http://lkml.kernel.org/r/1436428847-8886-3-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* PCI/MSI: Rename write_msi_msg() to pci_write_msi_msg()Jiang Liu2014-11-231-1/+1
| | | | | | | | | | | | | Rename write_msi_msg() to pci_write_msi_msg() to mark it as PCI specific. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* PCI/MSI: Remove "pos" from the struct msi_desc msi_attribYijing Wang2014-10-011-4/+2
| | | | | | | | | | "msi_attrib.pos" is only used for MSI (not MSI-X), and we already cache the MSI capability offset in "dev->msi_cap". Remove "pos" from the struct msi_attrib and use "dev->msi_cap" directly. [bhelgaas: changelog, fix whitespace] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* MIPS: Octeon: Add PCIe2 support in arch_setup_msi_irq()Eunbong Song2014-05-281-0/+6
| | | | | | | | | | | | In arch_setup_msi_irq(), there is no case for PCIe2. So board which have PCIe2 functionality fails to boot with "Kernel panic - not syncing: arch_setup_msi_irq: Invalid octeon_dma_bar_type" message. This patch solve this problem. Signed-off-by: Eunbong Song <eunb.song@samsung.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6747/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Fix fall through on bar type OCTEON_DMA_BAR_TYPE_SMALLColin Ian King2014-03-151-0/+1
| | | | | | | | | | | | | | Bar type OCTEON_DMA_BAR_TYPE_SMALL assigns lo and hi addresses and then falls through to OCTEON_DMA_BAR_TYPE_BIG that re-assignes lo and hi addresses with totally different values. Add a break so we don't fall through. Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6529/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix up inconsistency in panic() string argument.Ralf Baechle2011-12-071-1/+1
| | | | | | | | Panic() invokes printk() to add a \n internally, so panic arguments should not themselves end in \n. Panic invocations in arch/mips and elsewhere are inconsistently sometimes terminating in \n, sometimes not. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Convert the irq functions to the new namesThomas Gleixner2011-03-291-2/+2
| | | | | | Scripted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* MIPS: Octeon: Rewrite interrupt handling code.David Daney2011-03-291-10/+10
| | | | | | | | | | | | | | | | | This includes conversion to new style irq_chip functions, and correctly enabling/disabling per-CPU interrupts. The hardware interrupt bit to irq number mapping is now done with a flexible map, instead of by bit twiddling the irq number. [ tglx: Adjusted to new irq_cpu_on/offline callbacks and __irq_set_affinity_lock ] Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: ralf@linux-mips.org LKML-Reference: <1301081931-11240-5-git-send-email-ddaney@caviumnetworks.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* MIPS: Octeon: Disallow MSI-X interrupt and fall back to MSI interrupts.Chandrakala Chavva2010-08-051-0/+28
| | | | | | | | | | | | | MSI-X interrupts are not supported yet for Octeon, return error if MSI-X interrupts are requested by driver so that the driver will fall back to use MSI interrupts. Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: David Daney <ddaney@caviumnetworks.com> Patchwork: https://patchwork.linux-mips.org/patch/1506/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
* MIPS: Octeon: Support 256 MSI on PCIeDavid Daney2010-08-051-117/+177
| | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1507/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Make MSI use handle_simple_irq().David Daney2010-08-051-46/+15
| | | | | | | | | | | | | | The use of handle_percpu_irq() is not really what we want for MSI, use handle_simple_irq() instead. This is probably the prototypical case for using handle_simple_irq(), because all the MSIs are dispatched from the root interrupt service routine. Also since the base IRQ is not shared, don't pass IRQF_SHARED. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1488/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Get rid of a bunch of MSI IRQ number definitions.David Daney2010-08-051-2/+2
| | | | | | | | | | MSI IRQ numbers are allocated dynamically, so there is no reason to have all these static definitions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1487/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Move MSI code out of octeon-irq.c.David Daney2010-08-051-2/+88
| | | | | | | | | | Put all the MSI code in one place (msi-octeon.c). This simplifies octeon-irq.c and gets rid of some ugly #ifdefs Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1484/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Reorganize Cavium OCTEON PCI support.David Daney2009-07-031-0/+288
Move the cavium PCI files to the arch/mips/pci directory. Also cleanup comment formatting and code layout. Code from pci-common.c, was moved into other files. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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