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* mips: use the the PCI controller's io_map_baseMichael S. Tsirkin2012-01-312-2/+3
| | | | | | | | | | | | | | | commit eab90291d35438bcebf7c3dc85be66d0f24e3002 (mips: switch to GENERIC_PCI_IOMAP) failed to take into account the PCI controller's io_map_base for mapping IO BARs. This also caused a new warning on mips. Fix this, without re-introducing code duplication, by setting NO_GENERIC_PCI_IOPORT_MAP and supplying a mips-specific __pci_ioport_map. Reported-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* Merge branch 'for-linus' of ↵Linus Torvalds2012-01-172-8/+17
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/viro/audit * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/audit: (29 commits) audit: no leading space in audit_log_d_path prefix audit: treat s_id as an untrusted string audit: fix signedness bug in audit_log_execve_info() audit: comparison on interprocess fields audit: implement all object interfield comparisons audit: allow interfield comparison between gid and ogid audit: complex interfield comparison helper audit: allow interfield comparison in audit rules Kernel: Audit Support For The ARM Platform audit: do not call audit_getname on error audit: only allow tasks to set their loginuid if it is -1 audit: remove task argument to audit_set_loginuid audit: allow audit matching on inode gid audit: allow matching on obj_uid audit: remove audit_finish_fork as it can't be called audit: reject entry,always rules audit: inline audit_free to simplify the look of generic code audit: drop audit_set_macxattr as it doesn't do anything audit: inline checks for not needing to collect aux records audit: drop some potentially inadvisable likely notations ... Use evil merge to fix up grammar mistakes in Kconfig file. Bad speling and horrible grammar (and copious swearing) is to be expected, but let's keep it to commit messages and comments, rather than expose it to users in config help texts or printouts.
| * audit: inline audit_syscall_entry to reduce burden on archsEric Paris2012-01-171-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Every arch calls: if (unlikely(current->audit_context)) audit_syscall_entry() which requires knowledge about audit (the existance of audit_context) in the arch code. Just do it all in static inline in audit.h so that arch's can remain blissfully ignorant. Signed-off-by: Eric Paris <eparis@redhat.com>
| * Audit: push audit success and retcode into arch ptrace.hEric Paris2012-01-172-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The audit system previously expected arches calling to audit_syscall_exit to supply as arguments if the syscall was a success and what the return code was. Audit also provides a helper AUDITSC_RESULT which was supposed to simplify things by converting from negative retcodes to an audit internal magic value stating success or failure. This helper was wrong and could indicate that a valid pointer returned to userspace was a failed syscall. The fix is to fix the layering foolishness. We now pass audit_syscall_exit a struct pt_reg and it in turns calls back into arch code to collect the return value and to determine if the syscall was a success or failure. We also define a generic is_syscall_success() macro which determines success/failure based on if the value is < -MAX_ERRNO. This works for arches like x86 which do not use a separate mechanism to indicate syscall failure. We make both the is_syscall_success() and regs_return_value() static inlines instead of macros. The reason is because the audit function must take a void* for the regs. (uml calls theirs struct uml_pt_regs instead of just struct pt_regs so audit_syscall_exit can't take a struct pt_regs). Since the audit function takes a void* we need to use static inlines to cast it back to the arch correct structure to dereference it. The other major change is that on some arches, like ia64, MIPS and ppc, we change regs_return_value() to give us the negative value on syscall failure. THE only other user of this macro, kretprobe_example.c, won't notice and it makes the value signed consistently for the audit functions across all archs. In arch/sh/kernel/ptrace_64.c I see that we were using regs[9] in the old audit code as the return value. But the ptrace_64.h code defined the macro regs_return_value() as regs[3]. I have no idea which one is correct, but this patch now uses the regs_return_value() function, so it now uses regs[3]. For powerpc we previously used regs->result but now use the regs_return_value() function which uses regs->gprs[3]. regs->gprs[3] is always positive so the regs_return_value(), much like ia64 makes it negative before calling the audit code when appropriate. Signed-off-by: Eric Paris <eparis@redhat.com> Acked-by: H. Peter Anvin <hpa@zytor.com> [for x86 portion] Acked-by: Tony Luck <tony.luck@intel.com> [for ia64] Acked-by: Richard Weinberger <richard@nod.at> [for uml] Acked-by: David S. Miller <davem@davemloft.net> [for sparc] Acked-by: Ralf Baechle <ralf@linux-mips.org> [for mips] Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [for ppc]
* | Merge branch 'for-next' of git://git.infradead.org/users/dhowells/linux-headersLinus Torvalds2012-01-142-4/+10
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-next' of git://git.infradead.org/users/dhowells/linux-headers: UAPI: Split trivial #if defined(__KERNEL__) && X conditionals UAPI: Don't have a #elif clause in a __KERNEL__ guard in linux/soundcard.h UAPI: Fix AHZ multiple inclusion when __KERNEL__ is removed UAPI: Make linux/patchkey.h easier to parse UAPI: Fix nested __KERNEL__ guards in video/edid.h UAPI: Alter the S390 asm include guards to be recognisable by the UAPI splitter UAPI: Guard linux/cuda.h UAPI: Guard linux/pmu.h UAPI: Guard linux/isdn_divertif.h UAPI: Guard linux/sound.h UAPI: Rearrange definition of HZ in asm-generic/param.h UAPI: Make FRV use asm-generic/param.h UAPI: Make M32R use asm-generic/param.h UAPI: Make MN10300 use asm-generic/param.h UAPI: elf_read_implies_exec() is a kernel-only feature - so hide from userspace UAPI: Don't include linux/compat.h in sparc's asm/siginfo.h UAPI: Fix arch/mips/include/asm/Kbuild to have separate header-y lines
| * | UAPI: Split trivial #if defined(__KERNEL__) && X conditionalsDavid Howells2011-12-131-3/+7
| | | | | | | | | | | | | | | | | | | | | Split trivial #if defined(__KERNEL__) && X conditionals to make automated disintegration easier. Signed-off-by: David Howells <dhowells@redhat.com>
| * | UAPI: Fix arch/mips/include/asm/Kbuild to have separate header-y linesDavid Howells2011-12-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix arch/mips/include/asm/Kbuild to have a separate header-y line for each header to make them easier to relocate individually as part of the UAPI header split. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Ralf Baechle <ralf@linux-mips.org>
* | | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2012-01-14313-5966/+42528
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (119 commits) MIPS: Delete unused function add_temporary_entry. MIPS: Set default pci cache line size. MIPS: Flush huge TLB MIPS: Octeon: Remove SYS_SUPPORTS_HIGHMEM. MIPS: Octeon: Add support for OCTEON II PCIe MIPS: Octeon: Update PCI Latency timer and enable more error reporting. MIPS: Alchemy: Update cpu-feature-overrides MIPS: Alchemy: db1200: Improve PB1200 detection. MIPS: Alchemy: merge Au1000 and Au1300-style IRQ controller code. MIPS: Alchemy: chain IRQ controllers to MIPS IRQ controller MIPS: Alchemy: irq: register pm at irq init time MIPS: Alchemy: Touchscreen support on DB1100 MIPS: Alchemy: Hook up IrDA on DB1000/DB1100 net/irda: convert au1k_ir to platform driver. MIPS: Alchemy: remove unused board headers MTD: nand: make au1550nd.c a platform_driver MIPS: Netlogic: Mark Netlogic chips as SMT capable MIPS: Netlogic: Add support for XLP 3XX cores MIPS: Netlogic: Merge some of XLR/XLP wakup code MIPS: Netlogic: Add default XLP config. ... Fix up trivial conflicts in arch/mips/kernel/{perf_event_mipsxx.c, traps.c} and drivers/tty/serial/Makefile
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| *-----------------. \ \ Merge branches 'next/ar7', 'next/ath79', 'next/bcm63xx', 'next/bmips', ↵Ralf Baechle2012-01-11174-1957/+36201
| |\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'next/cavium', 'next/generic', 'next/kprobes', 'next/lantiq', 'next/perf' and 'next/raza' into mips-for-linux-next
| | | | | | | | | | | * | | MIPS: Netlogic: Mark Netlogic chips as SMT capableHillf Danton2011-12-071-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Netlogic XLR chip has multiple cores. Each core includes four integrated hardware threads, and they share L1 data and instruction caches. If the chip is marked to be SMT capable, scheduler then could do more, say, idle load balancing. Changes are now confined only to the code of XLR, and hardware is probed to get core ID for correct setup. [jayachandranc: simplified and adapted for new merged XLR/XLP code] Signed-off-by: Hillf Danton <dhillf@gmail.com> Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2972/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: Add support for XLP 3XX coresJayachandran C2011-12-073-12/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new processor ID to asm/cpu.h and kernel/cpu-probe.c. Update to new CPU frequency detection code which works on XLP 3XX and 8XX. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2971/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: Merge some of XLR/XLP wakup codeJayachandran C2011-12-0713-230/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a common NMI and reset handler in smpboot.S and use this for both XLR and XLP. In the earlier code, the woken up CPUs would busy wait until released, switch this to wakeup by NMI. The initial wakeup code or XLR and XLP are differ since they are started from different bootloaders (XLP from u-boot and XLR from netlogic bootloader). But in both platforms the woken up CPUs wait and are released by sending an NMI. Add support for starting XLR and XLP in 1/2/4 threads per core. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2970/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: Add default XLP config.Jayachandran C2011-12-071-0/+570
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2969/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: Add XLP makefiles and configJayachandran C2011-12-077-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add CPU_XLP and NLM_XLR_BOARD to arch/mips/Kconfig for Netlogic XLP boards - Update mips Makefiles to add XLP Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2968/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: Add XLP platform files for XLP SoCJayachandran C2011-12-0716-4/+1938
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Update common files to support XLP. - Add arch/mips/include/asm/netlogic/xlp-hal for register definitions and access macros - Add arch/mips/netlogic/xlp/ for XLP specific files. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2967/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: XLP CPU support.Jayachandran C2011-12-075-8/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Netlogic's XLP MIPS SoC. This patch adds: * XLP processor ID in cpu_probe.c and asm/cpu.h * XLP case to asm/module.h * CPU_XLP case to mm/tlbex.c * minor change to r4k cache handling to ignore XLP secondary cache * XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2966/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: Update default configJayachandran C2011-12-071-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Enable PCI and MSI by default - Update cross compile tool-chain and rootfs Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2965/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: Move code common with XLP to common/Jayachandran C2011-12-0719-441/+698
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move code that can be shared with XLP (irq.c, smp.c, time.c and xlr_console.c) to arch/mips/netlogic/common - Add asm/netlogic/haldefs.h and asm/netlogic/common.h for common and io functions shared with XLP - remove type 'nlm_reg_t *' and use uint64_t for mmio offsets - Move XLR specific code in smp.c to xlr/wakeup.c - Move XLR specific PCI code from irq.c to mips/pci/pci-xlr.c - Provide API for pic functions called from common/irq.c Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2964/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: No need to set -Werror in mips/xlrJayachandran C2011-12-071-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The -Werror compilation flag is already set for arch/mips - it can be removed from arch/mips/xlr/Makefile Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2963/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: Use CPU_XLR instead of NLM_XLRJayachandran C2011-12-074-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU_XLR config variable is sufficient for XLR compilation, the variable NLM_XLR can be removed. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2962/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: Style fixes for PlatformJayachandran C2011-12-071-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use platform- variable for xlr - Load address common for all netlogic chips Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2961/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: Add basic MSI support for XLR/XLSGanesan Ramalingam2011-12-074-1/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic support for MSI. Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com> Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2730/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: Avoid unnecessary cache flushesJayachandran C2011-12-071-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XLR dcache is fully coherent across CPUs, so avoid unnecessary dcache flushes. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2729/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: add r4k_wait as the cpu_waitJayachandran C2011-12-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use r4k_wait as the CPU wait function for XLR/XLS processors. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | | * | | MIPS: Netlogic: Change load addressJayachandran C2011-12-071-1/+1
| | | | | | | | | | |/ / / | | | | | | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move load address from 0x84000000 to 0x80100000 to avoid wasting memory. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | * | | MIPS/Perf-events: Cleanup event->destroy at event initDeng-Cheng Zhu2011-12-071-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the code by changing the place of event->destroy(). Signed-off-by: Deng-Cheng Zhu <dczhu@mips.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: David Daney <david.daney@cavium.com> Cc: Eyal Barzilay <eyal@mips.com> Cc: Zenon Fortuna <zenon@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/3109/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | * | | MIPS/Perf-events: Remove pmu and event state checking in validate_event()Deng-Cheng Zhu2011-12-071-15/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Why removing pmu checking: Since 3.2-rc1, when arch level event init is called, the event is already connected to its PMU. Also, validate_event() is _only_ called by validate_group() in event init, so there is no need of checking or temporarily assigning event pmu during validate_group(). Why removing event state checking: Events could be created in PERF_EVENT_STATE_OFF (attr->disabled == 1), when these events go through this checking, validate_group() does dummy work. But we do need to do group scheduling emulation for them in event init. Again, validate_event() is _only_ called by validate_group(). Reference: http://www.spinics.net/lists/mips/msg42190.html Signed-off-by: Deng-Cheng Zhu <dczhu@mips.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: David Daney <david.daney@cavium.com> Cc: Eyal Barzilay <eyal@mips.com> Cc: Zenon Fortuna <zenon@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/3108/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | * | | MIPS/Perf-events: Remove erroneous check on active_eventsDeng-Cheng Zhu2011-12-071-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port the following patch for ARM by Mark Rutland: - 57ce9bb39b476accf8fba6e16aea67ed76ea523d ARM: 6902/1: perf: Remove erroneous check on active_events When initialising a PMU, there is a check to protect against races with other CPUs filling all of the available event slots. Since armpmu_add checks that an event can be scheduled, we do not need to do this at initialisation time. Furthermore the current code is broken because it assumes that atomic_inc_not_zero will unconditionally increment active_counts and then tries to decrement it again on failure. This patch removes the broken, redundant code. Signed-off-by: Deng-Cheng Zhu <dczhu@mips.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: David Daney <david.daney@cavium.com> Cc: Eyal Barzilay <eyal@mips.com> Cc: Zenon Fortuna <zenon@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/3106/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | | | * | | MIPS/Perf-events: Don't do validation on raw eventsDeng-Cheng Zhu2011-12-071-32/+2
| | | | | | | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS licensees may want to modify performance counters to count extra events. Also, now that the user is working on raw events, the manual is being used for sure. And feeding unsupported events shouldn't cause hardware failure and the like. [ralf@linux-mips.org: performance events also being used in internal performance evaluation and have a tendency to change as the micro- architecture evolves, even for minor revisions that may not be distinguishable by PrID. It's not very practicable to maintain a list of all events and there is no real benefit.] Signed-off-by: Deng-Cheng Zhu <dczhu@mips.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: David Daney <david.daney@cavium.com> Cc: Eyal Barzilay <eyal@mips.com> Cc: Zenon Fortuna <zenon@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/3107/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | * | | | MIPS Kprobes: Support branch instructions probingManeesh Soni2011-12-072-33/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support for kprobes on branch instructions. The branch instruction at the probed address is actually emulated and not executed out-of-line like other normal instructions. Instead the delay-slot instruction is copied and single stepped out of line. At the time of probe hit, the original branch instruction is evaluated and the target cp0_epc is computed similar to compute_retrun_epc(). It is also checked if the delay slot instruction can be skipped, which is true if there is a NOP in delay slot or branch is taken in case of branch likely instructions. Once the delay slot instruction is single stepped the normal execution resume with the cp0_epc updated the earlier computed cp0_epc as per the branch instructions. Signed-off-by: Maneesh Soni <manesoni@cisco.com> Signed-off-by: Victor Kamensky <kamensky@cisco.com> Cc: David Daney <david.daney@cavium.com> Cc: ananth@in.ibm.com Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2914/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | * | | | MIPS Kprobes: Refactor branch emulationManeesh Soni2011-12-073-45/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch refactors MIPS branch emulation code so as to allow skipping delay slot instruction in case of branch likely instructions when branch is not taken. This is useful for keeping the code common for use cases like kprobes where one would like to handle the branch instructions keeping the delay slot instuction also in picture for branch likely instructions. Also allow emulation when instruction to be decoded is not at pt_regs->cp0_epc as in case of kprobes where pt_regs->cp0_epc points to the breakpoint instruction. The patch also exports the function for modules. Signed-off-by: Maneesh Soni <manesoni@cisco.com> Signed-off-by: Victor Kamensky <kamensky@cisco.com> Cc: David Daney <david.daney@cavium.com> Cc: ananth@in.ibm.com Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2913/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | * | | | MIPS Kprobes: Deny probes on ll/sc instructionsManeesh Soni2011-12-071-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As ll/sc instruction are for atomic read-modify-write operations, allowing probes on top of these insturctions is a bad idea. Signed-off-by: Victor Kamensky <kamensky@cisco.com> Signed-off-by: Maneesh Soni <manesoni@cisco.com> Cc: David Daney <david.daney@cavium.com> Cc: ananth@in.ibm.com Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2912/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | * | | | MIPS Kprobes: Fix OOPS in arch_prepare_kprobe()Maneesh Soni2011-12-071-3/+12
| | | | | | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the arch_prepare_kprobe() on MIPS when it tries to find the instruction at the previous address to the probed address. The oops happens when the probed address is the first address in a kernel module and there is no previous address. The patch uses probe_kernel_read() to safely read the previous instruction. CPU 3 Unable to handle kernel paging request at virtual address ffffffffc0211ffc, epc == ffffffff81113204, ra == ffffffff8111511c Oops[#1]: Cpu 3 $ 0 : 0000000000000000 0000000000000001 ffffffffc0212000 0000000000000000 $ 4 : ffffffffc0220030 0000000000000000 0000000000000adf ffffffff81a3f898 $ 8 : ffffffffc0220030 ffffffffffffffff 000000000000ffff 0000000000004821 $12 : 000000000000000a ffffffff81105ddc ffffffff812927d0 0000000000000000 $16 : ffffffff81a40000 ffffffffc0220030 ffffffffc0220030 ffffffffc0212660 $20 : 0000000000000000 0000000000000008 efffffffffffffff ffffffffc0220000 $24 : 0000000000000002 ffffffff8139f5b0 $28 : a800000072adc000 a800000072adfca0 ffffffffc0220000 ffffffff8111511c Hi : 0000000000000000 Lo : 0000000000000000 epc : ffffffff81113204 arch_prepare_kprobe+0x1c/0xe8 Tainted: P ra : ffffffff8111511c register_kprobe+0x33c/0x730 Status: 10008ce3 KX SX UX KERNEL EXL IE Cause : 00800008 BadVA : ffffffffc0211ffc PrId : 000d9008 (Cavium Octeon II) Modules linked in: bpa_mem crashinfo pds tun cpumem ipv6 exportfs nfsd OOBnd(P) OOBhal(P) cvmx_mdio cvmx_gpio aipcmod(P) mtsmod procfs(P) utaker_mod dplr_pci hello atomicm_foo [last unloaded: sysmgr_hb] Process stapio (pid: 5603, threadinfo=a800000072adc000, task=a8000000722e0438, tls=000000002b4bcda0) Stack : ffffffff81a40000 ffffffff81a40000 ffffffffc0220030 ffffffff8111511c ffffffffc0218008 0000000000000001 ffffffffc0218008 0000000000000001 ffffffffc0220000 ffffffffc021efe8 1000000000000000 0000000000000008 efffffffffffffff ffffffffc0220000 ffffffffc0220000 ffffffffc021d500 0000000000000022 0000000000000002 1111000072be02b8 0000000000000000 00000000000015e6 00000000000015e6 00000000007d0f00 a800000072be02b8 0000000000000000 ffffffff811d16c8 a80000000382e3b0 ffffffff811d5ba0 ffffffff81b0a270 ffffffff81b0a270 ffffffffc0212000 0000000000000013 ffffffffc0220030 ffffffffc021ed00 a800000089114c80 000000007f90d590 a800000072adfe38 a800000089114c80 0000000010020000 0000000010020000 ... Call Trace: [<ffffffff81113204>] arch_prepare_kprobe+0x1c/0xe8 [<ffffffff8111511c>] register_kprobe+0x33c/0x730 [<ffffffffc021d500>] _stp_ctl_write_cmd+0x8e8/0xa88 [atomicm_foo] [<ffffffff812925cc>] vfs_write+0xb4/0x178 [<ffffffff81292828>] SyS_write+0x58/0x148 [<ffffffff81103844>] handle_sysn32+0x44/0x84 Code: ffb20010 ffb00000 dc820028 <8c44fffc> 8c500000 0c4449e0 0004203c 14400029 3c048199 Signed-off-by: Maneesh Soni <manesoni@cisco.com> Signed-off-by: Victor Kamensky <kamensky@cisco.com> Cc: David Daney <david.daney@cavium.com> Cc: ananth@in.ibm.com Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2915/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | | | | MIPS: Octeon: Remove SYS_SUPPORTS_HIGHMEM.Chandrakala Chavva2011-12-081-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only 64-bit kernels are supported, no need for SYS_SUPPORTS_HIGHMEM Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2988/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | | | | MIPS: Octeon: Add support for OCTEON II PCIeDavid Daney2011-12-081-326/+1023
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OCTEON II SOCs have a different PCIe implementation than is present in OCTEON Plus. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2985/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | | | | MIPS: Octeon: Update PCI Latency timer and enable more error reporting.David Daney2011-12-081-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2987/ Patchwork: https://patchwork.linux-mips.org/patch/3161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | | | | MIPS: Octeon: Update DMA mapping operations for OCTEON II processors.David Daney2011-12-072-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OCTEON II has a new dma to phys mapping method for PCIe. Define OCTEON_DMA_BAR_TYPE_PCIE2 to denote this case, and handle it. OCTEON II also needs a swiotlb if the OHCI USB driver is enabled, so allocate this too. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2983/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | | | | MIPS: Octeon: Update feature test functions for new chips and features.David Daney2011-12-072-30/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cvmx.h was rearranged to fix include file ordering problems, but there is no change other than moving some definitions around. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2984/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | | | | MIPS: Octeon: Update SOC PCI related register definitions for new chips.David Daney2011-12-077-83/+4909
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2986/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | | | | MIPS: Octeon: Rearrange CVMX files in preperation for device treeDavid Daney2011-12-0711-24/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: devel@driverdev.osuosl.org Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Patchwork: https://patchwork.linux-mips.org/patch/2941/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | | | | MIPS: Octeon: Update bootloader board type constants.David Daney2011-12-073-3/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many new types of boards exist, so lets recognize them. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: devel@driverdev.osuosl.org Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Patchwork: https://patchwork.linux-mips.org/patch/2940/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | | | | MIPS: Octeon: Move some Ethernet support files out of staging.David Daney2011-12-0752-5/+21643
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: devel@driverdev.osuosl.org Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Patchwork: https://patchwork.linux-mips.org/patch/2942/ Patchwork: https://patchwork.linux-mips.org/patch/3012/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | | | | MIPS: Oceton: Update model detection code for new chips.David Daney2011-12-073-188/+1179
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several newer chips were not covered, update the code to detect them. This necessitates updating cvmx-mio-defs.h as well, because it has new and required definitions. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2939/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | | | | MIPS: Octeon: Update struct cvmx_bootinfo to v3.David Daney2011-12-071-2/+8
| | | | | | | |/ / / | | | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bootloaders can pass version 3 of this structure. Add the new fields so we can support the Device Tree. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2938/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | * | | | | MIPS: BMIPS: Add SMP support code for BMIPS43xx/BMIPS5000Kevin Cernekee2011-12-074-0/+717
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initial commit of BMIPS SMP support code. Smoke-tested on a variety of BMIPS4350, BMIPS4380, and BMIPS5000 platforms. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2977/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | * | | | | MIPS: Add board_ebase_setup()Kevin Cernekee2011-12-072-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some systems need to relocate the MIPS exception vector base during trap initialization. Add a hook to make this possible. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2959/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | * | | | | MIPS: Add NMI notifierKevin Cernekee2011-12-072-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the board support code to register a raw notifier callback for NMI, similar to what is done for CU2 exceptions. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2958/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | * | | | | MIPS: BMIPS: Introduce bmips.hKevin Cernekee2011-12-071-0/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bmips.h contains BMIPS definitions that are useful for SMP, vector relocation, performance counters, etc. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2973/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | * | | | | MIPS: BMIPS: Add set/clear CP0 macros for BMIPS operationsKevin Cernekee2011-12-071-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several BMIPS-specific CP0 registers are used for SMP boot and other operations. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2956/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | * | | | | MIPS: BMIPS: Add CFLAGS, Makefile entries for BMIPSKevin Cernekee2011-12-073-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CONFIG_CPU_BMIPS* in all of the right places, so that BMIPS kernel images will compile and run. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2955/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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