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| | * MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6Markos Chandras2015-02-173-2/+15
| | | | | | | | | | | | | | | | | | | | | The MIPS R6 JR instruction is an alias to the JALR one, so it may need emulation for non-R6 userlands. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: mm: scache: Add secondary cache support for MIPS R6 coresMarkos Chandras2015-02-172-2/+4
| | | | | | | | | | | | | | | | | | | | | The secondary cache initialization and configuration code is processor specific so we need to handle MIPS R6 cores as well. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: mm: c-r4k: Set the correct ISA levelMarkos Chandras2015-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The local_r4k_flush_cache_sigtramp function uses the 'cache' instruction inside an asm block. However, MIPS R6 changed the opcode for the cache instruction and as a result of which we need to set the correct ISA level. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instructionLeonid Yegoshin2015-02-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS uses the cpu_has_mips_r2_exec_hazard macro to determine whether the EHB instruction is available or not. This is necessary for MIPS R6 which also supports the EHB instruction. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: mm: page: Add MIPS R6 supportMarkos Chandras2015-02-171-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS R6 pref instruction only has 9 bits for the immediate field so skip the micro-assembler PREF instruction if the offset does not fit in 9 bits. Moreover, bit 30 (Pref_PrepareForStore) is no longer valid in MIPS R6, so we change the default for all MIPS R6 processors to bit 5 (Pref_StoreStreamed). Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: lib: memset: Add MIPS R6 supportLeonid Yegoshin2015-02-171-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS R6 dropped the unaligned load and store instructions so we need to re-write this part of the code for R6 to store one byte at a time. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: lib: memcpy: Add MIPS R6 supportLeonid Yegoshin2015-02-171-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS R6 does not support the unaligned load and store instructions so we add a special MIPS R6 case to copy one byte at a time if we need to read/write to unaligned memory addresses. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: kernel: syscall: Set the appropriate ISA level for MIPS R6Markos Chandras2015-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | MIPS R6 changed the opcodes for LL/SC instructions so we need to set the appropriate ISA level. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: kernel: unaligned: Add support for the MIPS R6Leonid Yegoshin2015-02-171-4/+386
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The load/store unaligned instructions have been removed in MIPS R6 so we need to re-implement the related macros using the regular load/store instructions. Moreover, the load/store from coprocessor 2 instructions have been reallocated in Release 6 so we will handle them in the emulator instead. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: kernel: cps-vec: Replace "addi" with "addiu"Markos Chandras2015-02-171-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "addi" instruction will trap on overflows which is not something we need in this code, so we replace that with "addiu". Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00430.html Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: <stable@vger.kernel.org> # v3.15+ Cc: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: kernel: genex: Set correct ISA levelMarkos Chandras2015-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | The jr instruction opcode has changed in R6 so make sure the correct ISA level is set prior using that instruction. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: kernel: r4k_fpu: Add support for MIPS R6Leonid Yegoshin2015-02-171-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the MIPS R6 related preprocessor definitions for FPU signal related functions. MIPS R6 only has FR=1 so avoid checking that bit on the C0/Status register. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: kernel: r4k_switch: Add support for MIPS R6Leonid Yegoshin2015-02-172-11/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the MIPS R6 related preprocessor definitions for save/restore FPU related functions. We also set the appropriate ISA level so the final return instruction "jr ra" will produce the correct opcode on R6. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: kernel: traps: Add MIPS R6 related definitionsLeonid Yegoshin2015-02-171-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add MIPS R6 support to cache and ftlb exceptions, as well as to the hwrena and ebase register configuration. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: kernel: proc: Add MIPS R6 support to /proc/cpuinfoMarkos Chandras2015-02-172-1/+10
| | | | | | | | | | | | | | | | | | | | | Print 'mips64r6' and/or 'mips32r6' if the kernel is running on a MIPS R6 core. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: kernel: entry.S: Add MIPS R6 related definitionsMarkos Chandras2015-02-171-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The instruction hazard barrier in the form of: jr.hb ra nop is valid on MIPS R6 as well. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: kernel: cpu-probe.c: Add support for MIPS R6Leonid Yegoshin2015-02-171-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MIPS R6 support when decoding the config0 c0 register. Also add MIPS R6 support when examining the ebase c0 register to get the core number and when getting the shadow set number from the srsctl c0 register. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: kernel: cevt-r4k: Add MIPS R6 to the c0_compare_interrupt handlerLeonid Yegoshin2015-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Just like MIPS R2, in MIPS R6 it is possible to determine if a timer interrupt has happened or not. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: kernel: cpu-bugs64: Do not check R6 cores for existing 64-bit bugsLeonid Yegoshin2015-02-171-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current HW bugs checked in cpu-bugs64, do not apply to R6 cores and they cause compilation problems due to removed <R6 instructions, so do not check for them for the time being. Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: local: Set the appropriate ISA level for MIPS R6Markos Chandras2015-02-171-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | MIPS R6 changed the opcodes for LL/SC instructions so we need to set the appropriate ISA level. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: spinlock: Replace "sub" instruction with "addiu"Markos Chandras2015-02-171-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | "sub $reg, imm" is not a real MIPS instruction. The assembler can replace that with "addi $reg, -imm". However, addi has been removed from R6, so we replace the "sub" instruction with the "addiu" one. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: futex: Set the appropriate ISA level for MIPS R6Markos Chandras2015-02-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | MIPS R6 changed the opcodes for LL/SC instructions so we need to set the appropriate ISA level. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: bitops: Update ISA constraints for MIPS R6 supportMarkos Chandras2015-02-171-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | MIPS R6 changed the opcodes for LL/SC instructions so we need to set the correct ISA level. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: atomic: Update ISA constraints for MIPS R6 supportMarkos Chandras2015-02-171-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | MIPS R6 changed the opcodes for LL/SC instructions so we need to set the correct ISA level. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: cmpxchg: Update ISA constraints for MIPS R6 supportMarkos Chandras2015-02-171-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | MIPS R6 changed the opcodes for LL/SC instructions so we need to set the correct ISA. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: Use the new "ZC" constraint for MIPS R6Markos Chandras2015-02-171-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | GCC versions supporting MIPS R6 use the ZC constraint to enforce a 9-bit offset for MIPS R6. We will use that for all MIPS R6 LL/SC instructions. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: Rename GCC_OFF12_ASM to GCC_OFF_SMALL_ASMMarkos Chandras2015-02-179-93/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | The GCC_OFF12_ASM macro is used for 12-bit immediate constrains but we will also use it for 9-bit constrains on MIPS R6 so we rename it to something more appropriate. Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: spram: Add new symbol for MIPS scratch pad storageMarkos Chandras2015-02-173-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS R6, just like MIPS R2, have scratch pad storage, so add a new symbol which is selected by MIPS R2 and R6. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00389.html Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: r4kcache: Add MIPS R6 cache unroll functionsMarkos Chandras2015-02-171-2/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS R6 changed the 'cache' instruction opcode and reduced the offset field to 8 bits. This means we now have to adjust the base register every 256 bytes and as a result of which we can no longer use the previous cache functions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: irqflags: Add MIPS R6 related definitionsMarkos Chandras2015-02-172-4/+5
| | | | | | | | | | | | | | | | | | Add the MIPS R6 related definitions to the IRQ related macros Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: hazards: Add MIPSR6 definitionsMarkos Chandras2015-02-171-4/+5
| | | | | | | | | | | | | | | | | | Add the MIPSR6 related definitions to MIPS hazards Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: cpu: Add MIPSR6 ISA definitionsLeonid Yegoshin2015-02-172-6/+20
| | | | | | | | | | | | | | | | | | | | | Add MIPS R6 to the ISA definitions Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: Use generic checksum functions for MIPS R6Markos Chandras2015-02-175-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following instructions have been removed from MIPS R6 ulw, ulh, swl, lwr, lwl, swr. However, all of them are used in the MIPS specific checksum implementation. As a result of which, we will use the generic checksum on MIPS R6 Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: asmmacro: Replace "add" instructions with "addu"Markos Chandras2015-02-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "add" instruction is actually a macro in binutils and depending on the size of the immediate it can expand to an "addi" instruction. However, the "addi" instruction traps on overflows which is not something we want on address calculation. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00121.html Cc: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: <stable@vger.kernel.org> # v3.15+ Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: asmmacro: Add MIPS R6 support to the simple EI/DI variantsLeonid Yegoshin2015-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | EI/DI instructions are available in MIPS R6 so add the needed definitions. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: stackframe: Do not preserve the HI/LO registers on MIPS R6Leonid Yegoshin2015-02-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HI/LO registers have been removed from MIPS R6. Instructions such as MULT and DIV have been replaced with a new pair of instructions for the HI/LO operations for example: MULT -> MUL, MUH DIV -> DIV, MOD So we avoid preserving the pre-R6 HI/LO registers in MIPS R6 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: module: define MODULE_PROC_FAMILY for MIPS R6Leonid Yegoshin2015-02-171-0/+4
| | | | | | | | | | | | | | | | | | | | | Define the MODULE_PROC_FAMILY for the MIPS R6 ISA. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: asm: compiler: Add new macros to set ISA and arch asm annotationsMarkos Chandras2015-02-171-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are certain places where the code uses .set mips32 or .set mips64 or .set arch=r4000. In preparation of MIPS R6 support, and in order to use as less #ifdefs as possible, we define new macros to set similar annotations for MIPS R6. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: mm: Add MIPS R6 instruction encodingsLeonid Yegoshin2015-02-162-3/+38
| | | | | | | | | | | | | | | | | | | | | | | | MIPS R6 defines new opcodes for ll, sc, cache and pref instructions so we need to take these into consideration in the micro-assembler. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: mm: uasm: Add signed 9-bit immediate related macrosLeonid Yegoshin2015-02-161-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | MIPS R6 redefines several instructions and reduces the immediate field to 9-bits so add related macros for the microassembler. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: Add build support for the MIPS R6 ISALeonid Yegoshin2015-02-162-4/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add build support for the latest revision (R6) of the MIPS ISA. microMIPS is not yet supported. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00386.html Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: Add MIPS generic QEMU probe supportLeonid Yegoshin2015-02-161-0/+5
| | | | | | | | | | | | | | | | | | | | | Add a case in cpu_probe_mips for the MIPS generic QEMU processor ID. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: Add cases for CPU_QEMU_GENERICLeonid Yegoshin2015-02-167-0/+13
| | | | | | | | | | | | | | | | | | | | | Add a CPU_QEMU_GENERIC case to various switch statements. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: Add generic QEMU PRid and cpu type identifiersLeonid Yegoshin2015-02-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Latest versions of QEMU added support for mips32r6-generic and mips64r6-generic cpu types so add related definitions in preparation of MIPS R6 support. This is also used for QEMU R2 generic cpus. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| | * MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGSMarkos Chandras2015-02-161-18/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to check the ASEs support against the core's CFLAGS instead of depending to the default -march option from the toolchain. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9180/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Export MSA functions used by lose_fpu(1) for KVMJames Hogan2015-02-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export the _save_msa asm function used by the lose_fpu(1) macro to GPL modules so that KVM can make use of it when it is built as a module. This fixes the following build error when CONFIG_KVM=m and CONFIG_CPU_HAS_MSA=y due to commit f798217dfd03 ("KVM: MIPS: Don't leak FPU/DSP to guest"): ERROR: "_save_msa" [arch/mips/kvm/kvm.ko] undefined! Fixes: f798217dfd03 (KVM: MIPS: Don't leak FPU/DSP to guest) Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/9261/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Export FP functions used by lose_fpu(1) for KVMJames Hogan2015-02-191-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export the _save_fp asm function used by the lose_fpu(1) macro to GPL modules so that KVM can make use of it when it is built as a module. This fixes the following build error when CONFIG_KVM=m due to commit f798217dfd03 ("KVM: MIPS: Don't leak FPU/DSP to guest"): ERROR: "_save_fp" [arch/mips/kvm/kvm.ko] undefined! Signed-off-by: James Hogan <james.hogan@imgtec.com> Fixes: f798217dfd03 (KVM: MIPS: Don't leak FPU/DSP to guest) Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.10+ Patchwork: https://patchwork.linux-mips.org/patch/9260/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: BCM3384: Fix outdated use of mips_cpu_intc_init()Kevin Cernekee2015-02-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function was renamed to mips_cpu_irq_of_init(), so fix it to avoid a compile error. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8834/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Provide correct siginfo_t.si_stimePetr Malat2015-02-192-37/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide correct siginfo_t.si_stime on MIPS64 Bug description: MIPS version of copy_siginfo() is not aware of alignment on platforms with 64-bit long integers, which leads to an incorrect si_stime passed to signal handlers, because the last element (si_stime) of _sifields._sigchld is not copied. If _MIPS_SZLONG is 64, then the _sifields starts at the offset of 4 * sizeof(int). Patch description: Use the generic copy_siginfo, which doesn't have this problem. Signed-off-by: Petr Malat <oss@malat.biz> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8671/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGSMarkos Chandras2015-02-191-18/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to check the ASEs support against the core's CFLAGS instead of depending to the default -march option from the toolchain. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9180/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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