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* powerpc/4xx: Fix typos in kexec config dependenciesSuzuki Poulose2011-11-161-1/+1
| | | | | | | | | | | | | Kexec is not supported on 47x. 47x is a variant of 44x with slightly different MMU and SMP support. There was a typo in the config dependency for kexec. This patch fixes the same. Signed-off-by: Suzuki K. Poulose <suzuki@in.ibm.com> Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Josh Boyer <jwboyer@gmail.com> Cc: linux ppc dev <linuxppc-dev@lists.ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/44x: Kexec support for PPC440X chipsetsSuzuki Poulose2011-08-111-0/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds kexec support for PPC440 based chipsets. This work is based on the KEXEC patches for FSL BookE. The FSL BookE patch and the code flow could be found at the link below: http://patchwork.ozlabs.org/patch/49359/ Steps: 1) Invalidate all the TLB entries except the one this code is run from 2) Create a tmp mapping for our code in the other address space and jump to it 3) Invalidate the entry we used 4) Create a 1:1 mapping for 0-2GiB in blocks of 256M 5) Jump to the new 1:1 mapping and invalidate the tmp mapping I have tested this patches on Ebony, Sequoia boards and Virtex on QEMU. You need kexec-tools commit e8b7939b1e or newer for ppc440x support, available at: git://git.kernel.org/pub/scm/utils/kernel/kexec/kexec-tools.git Signed-off-by: Suzuki Poulose <suzuki@in.ibm.com> Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Josh Boyer <jwboyer@gmail.com>
* powerpc: Fix 32-bit SMP buildJosh Boyer2011-05-201-1/+1
| | | | | | | | | | | | | Commit 69e3cea8d5fd526 ("powerpc/smp: Make start_secondary_resume available to all CPU variants") introduced start_secondary_resume to misc_32.S, however it uses a 64-bit instruction which is not valid on 32-bit platforms. Use 'stw' instead. Reported-by: Richard Cochran <richardcochran@gmail.com> Tested-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* powerpc/smp: Make start_secondary_resume available to all CPU variantsBenjamin Herrenschmidt2011-05-191-0/+11
| | | | | | This should fix SMP & Hotplug builds on FSL BookE and 476 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Remove second definition of STACK_FRAME_OVERHEADStephen Rothwell2010-11-291-0/+1
| | | | | | | | | Since STACK_FRAME_OVERHEAD is defined in asm/ptrace.h and that is ASSEMBER safe, we can just include that instead of going via asm-offsets.h. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/kexec: Adds correct calling convention for kexec purgatoryMatthew McClintock2010-08-311-0/+3
| | | | | | | | | | | | | | | | | | Call kexec purgatory code correctly. We were getting lucky before. If you examine the powerpc 32bit kexec "purgatory" code you will see it expects the following: >From kexec-tools: purgatory/arch/ppc/v2wrap_32.S -> calling convention: -> r3 = physical number of this cpu (all cpus) -> r4 = address of this chunk (master only) As such, we need to set r3 to the current core, r4 happens to be unused by purgatory at the moment but we go ahead and set it here as well Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Unconditionally enabled irq stacksChristoph Hellwig2010-06-151-2/+0
| | | | | | | | | | | Irq stacks provide an essential protection from stack overflows through external interrupts, at the cost of two additionals stacks per CPU. Enable them unconditionally to simplify the kernel build and prevent people from accidentally disabling them. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/kexec: Add support for FSL-BookESebastian Andrzej Siewior2010-05-241-0/+17
| | | | | | | | | | | | | | | | This adds support kexec on FSL-BookE where the MMU can not be simply switched off. The code borrows the initial MMU-setup code to create the identical mapping mapping. The only difference to the original boot code is the size of the mapping(s) and the executeable address. The kexec code maps the first 2 GiB of memory in 256 MiB steps. This should work also on e500v1 boxes. SMP support is still not available. (Kumar: Added minor change to build to ifdef CONFIG_PPC_STD_MMU_64 some code that was PPC64 specific) Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/47x: Base ppc476 supportDave Kleikamp2010-05-051-2/+7
| | | | | | | | | | | | | | | | This patch adds the base support for the 476 processor. The code was primarily written by Ben Herrenschmidt and Torez Smith, but I've been maintaining it for a while. The goal is to have a single binary that will run on 44x and 47x, but we still have some details to work out. The biggest is that the L1 cache line size differs on the two platforms, but it's currently a compile-time option. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/8xx: Start using dcbX instructions in various copy routinesJoakim Tjernlund2009-12-091-18/+0
| | | | | | | | Now that 8xx can fixup dcbX instructions, start using them where possible like every other PowerPc arch do. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Fix __flush_icache_range on 44xJosh Boyer2009-08-271-0/+7
| | | | | | | | | | | | | | | | The ptrace POKETEXT interface allows a process to modify the text pages of a child process being ptraced, usually to insert breakpoints via trap instructions. The kernel eventually calls copy_to_user_page, which in turn calls __flush_icache_range to invalidate the icache lines for the child process. However, this function does not work on 44x due to the icache being virtually indexed. This was noticed by a breakpoint being triggered after it had been cleared by ltrace on a 440EPx board. The convenient solution is to do a flash invalidate of the icache in the __flush_icache_range function. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/44x: Support 16K/64K base page sizes on 44xIlya Yanok2008-12-291-6/+6
| | | | | | | | | | | | | | | | | | This adds support for 16k and 64k page sizes on PowerPC 44x processors. The PGDIR table is much smaller than a page when using 16k or 64k pages (512 and 32 bytes respectively) so we allocate the PGDIR with kzalloc() instead of __get_free_pages(). One PTE table covers rather a large memory area when using 16k or 64k pages (32MB or 512MB respectively), so we can easily put FIXMAP and PKMAP in the area covered by one PTE table. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Vladimir Panfilov <pvr@emcraft.com> Signed-off-by: Ilya Yanok <yanok@emcraft.com> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc/mm: Split low level tlb invalidate for nohash processorsBenjamin Herrenschmidt2008-12-211-233/+0
| | | | | | | | | | | | | | | | | | | | | | | Currently, the various forms of low level TLB invalidations are all implemented in misc_32.S for 32-bit processors, in a fairly scary mess of #ifdef's and with interesting duplication such as a whole bunch of code for FSL _tlbie and _tlbia which are no longer used. This moves things around such that _tlbie is now defined in hash_low_32.S and is only used by the 32-bit hash code, and all nohash CPUs use the various _tlbil_* forms that are now moved to a new file, tlb_nohash_low.S. I moved all the definitions for that stuff out of include/asm/tlbflush.h as they are really internal mm stuff, into mm/mmu_decl.h The code should have no functional changes. I kept some variants inline for trivial forms on things like 40x and 8xx. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc/mm: Add SMP support to no-hash TLB handlingBenjamin Herrenschmidt2008-12-211-0/+9
| | | | | | | | | | | | | | | | This commit moves the whole no-hash TLB handling out of line into a new tlb_nohash.c file, and implements some basic SMP support using IPIs and/or broadcast tlbivax instructions. Note that I'm using local invalidations for D->I cache coherency. At worst, if another processor is trying to execute the same and has the old entry in its TLB, it will just take a fault and re-do the TLB flush locally (it won't re-do the cache flush in any case). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc/fsl-booke: Fix the miss interrupt restoreDave Liu2008-12-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit e5e774d8833de1a0037be2384efccadf16935675 powerpc/fsl-booke: Fix problem with _tlbil_va being interrupted introduce one issue. that casue the problem like this: Kernel BUG at c00b19fc [verbose debug info unavailable] Oops: Exception in kernel mode, sig: 5 [#1] MPC8572 DS Modules linked in: NIP: c00b19fc LR: c00b1c34 CTR: c0064e88 REGS: ef02b7b0 TRAP: 0700 Not tainted (2.6.28-rc8-00057-g1bda712) MSR: 00021000 <ME> CR: 44048028 XER: 20000000 TASK = ef02c000[1] 'init' THREAD: ef02a000 GPR00: 00000001 ef02b860 ef02c000 eec201a0 c0dec2c0 00000000 000078a1 00000400 GPR08: c00b4e40 000078a1 c048ec00 a1780000 44048028 ecd26917 00000001 ef02b948 GPR16: ffffffea 0000020c 00000000 00000000 00000003 0000000a 00000000 000078a1 GPR24: eec201a0 00000000 ed849000 00000400 ef02b95c 00000001 ef02b978 ef02b984 NIP [c00b19fc] __find_get_block+0x24/0x238 LR [c00b1c34] __getblk+0x24/0x2a0 Call Trace: [ef02b860] [c017b768] generic_make_request+0x290/0x328 (unreliable) [ef02b8b0] [c00b1c34] __getblk+0x24/0x2a0 [ef02b910] [c00b4ae4] __bread+0x14/0xf8 [ef02b920] [c00fc228] ext2_get_branch+0xf0/0x138 [ef02b940] [c00fcc88] ext2_get_block+0xb8/0x828 [ef02ba00] [c00bbdc8] do_mpage_readpage+0x188/0x808 [ef02bac0] [c00bc5b4] mpage_readpages+0xec/0x144 [ef02bb50] [c00fba38] ext2_readpages+0x24/0x34 [ef02bb60] [c006ade0] __do_page_cache_readahead+0x150/0x230 [ef02bbb0] [c0064bdc] filemap_fault+0x31c/0x3e0 [ef02bbf0] [c00728b8] __do_fault+0x60/0x5b0 [ef02bc50] [c0011e0c] do_page_fault+0x2d8/0x4c4 [ef02bd10] [c000ed90] handle_page_fault+0xc/0x80 [ef02bdd0] [c00c7adc] set_brk+0x74/0x9c [ef02bdf0] [c00c9274] load_elf_binary+0x70c/0x1180 [ef02be70] [c00945f0] search_binary_handler+0xa8/0x274 [ef02bea0] [c0095818] do_execve+0x19c/0x1d4 [ef02bed0] [c000766c] sys_execve+0x58/0x84 [ef02bef0] [c000e950] ret_from_syscall+0x0/0x3c [ef02bfb0] [c009c6fc] sys_dup+0x24/0x6c [ef02bfc0] [c0001e04] init_post+0xb0/0xf0 [ef02bfd0] [c046c1ac] kernel_init+0xcc/0xf4 [ef02bff0] [c000e6d0] kernel_thread+0x4c/0x68 Instruction dump: 4bffffa4 813f000c 4bffffac 9421ffb0 7c0802a6 7d800026 90010054 bf210034 91810030 7c0000a6 68008000 54008ffe <0f000000> 3d20c04e 3b29ffb8 38000008 The issue was the beqlr returns early but we haven't reenabled interrupts. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/fsl-booke: Fix problem with _tlbil_va being interruptedKumar Gala2008-12-131-0/+3
| | | | | | | | | | | | | | | | An example calling sequence which we did see: copy_user_highpage -> kmap_atomic -> flush_tlb_page -> _tlbil_va We got interrupted after setting up the MAS registers before the tlbwe and the interrupt handler that caused the interrupt also did a kmap_atomic (ide code) and thus on returning from the interrupt the MAS registers no longer contained the proper values. Since we dont save/restore MAS registers for normal interrupts we need to disable interrupts in _tlbil_va to ensure atomicity. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/fsl-booke: Fix synchronization bug w/local tlb invalidatesKumar Gala2008-11-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implemetation of _tlbil_pid() on Freescale Book-E cores needs an msync & isync after we flash invalidate the TLBs. This was causing the following oops reported by Sebastian Andrzej Siewior: VFS: Mounted root (nfs filesystem) readonly. Freeing unused kernel memory: 148k init BUG: sleeping function called from invalid context at /home/bigeasy/git/linux-2.6-powerpc/mm/mmap.c:234 in_atomic():1, irqs_disabled():0 Call Trace: [df189df0] [c0007160] show_stack+0x48/0x148 (unreliable) [df189e30] [c0029480] __might_sleep+0xf0/0x100 [df189e40] [c0070ac0] remove_vma+0x28/0x98 [df189e50] [c0070c1c] exit_mmap+0xec/0x128 [df189e80] [c002d2f4] mmput+0x54/0xec [df189ea0] [c0030b6c] exit_mm+0x10c/0x120 [df189ed0] [c003288c] do_exit+0x1ac/0x6e8 [df189f20] [c0032e48] do_group_exit+0x80/0xac [df189f40] [c000e9dc] ret_from_syscall+0x0/0x3c BUG: scheduling while atomic: udevd/956/0x10000002 Modules linked in: Call Trace: [df189df0] [c0007160] show_stack+0x48/0x148 (unreliable) [df189e30] [c002ac88] __schedule_bug+0x58/0x6c [df189e40] [c023e6cc] schedule+0xa8/0x4a8 [df189e90] [c002ad6c] __cond_resched+0x38/0x64 [df189ea0] [c023ebc8] _cond_resched+0x3c/0x58 [df189eb0] [c0030e70] put_files_struct+0x90/0xec [df189ed0] [c00328a8] do_exit+0x1c8/0x6e8 [df189f20] [c0032e48] do_group_exit+0x80/0xac [df189f40] [c000e9dc] ret_from_syscall+0x0/0x3c Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: Fix error path in kernel_thread functionJosh Poimboeuf2008-10-101-3/+5
| | | | | | | | | | | | | | The powerpc 32-bit and 64-bit kernel_thread functions don't properly propagate errors being returned by the clone syscall. (In the case of error, the syscall exit code returns a positive errno in r3 and sets the CR0[SO] bit.) This patch fixes that by negating r3 if CR0[SO] is set after the syscall. Signed-off-by: Josh Poimboeuf <jpoimboe@us.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Introduce local (non-broadcast) forms of tlb invalidatesKumar Gala2008-09-241-0/+54
| | | | | | | | | | | | | | | | | | | | Introduced a new set of low level tlb invalidate functions that do not broadcast invalidates on the bus: _tlbil_all - invalidate all _tlbil_pid - invalidate based on process id (or mm context) _tlbil_va - invalidate based on virtual address (ea + pid) On non-SMP configs _tlbil_all should be functionally equivalent to _tlbia and _tlbil_va should be functionally equivalent to _tlbie. The intent of this change is to handle SMP based invalidates via IPIs instead of broadcasts as the mechanism scales better for larger number of cores. On e500 (fsl-booke mmu) based cores move to using MMUCSR for invalidate alls and tlbsx/tlbwe for invalidate virtual address. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/kexec: Fix up KEXEC_CONTROL_CODE_SIZE missed during conversionPaul Collins2008-08-181-1/+1
| | | | | | | | | | | | | | | | | Commit 163f6876f5c3ff8215e900b93779e960a56b3694 missed one, resulting in the following compile error: AS arch/powerpc/kernel/misc_32.o arch/powerpc/kernel/misc_32.S: Assembler messages: arch/powerpc/kernel/misc_32.S:902: Error: unsupported relocation against KEXEC_CONTROL_CODE_SIZE make[2]: *** [arch/powerpc/kernel/misc_32.o] Error 1 make[1]: *** [arch/powerpc/kernel] Error 2 make: *** [vmlinux] Error 2 I grepped arch/ and found no further instances. Signed-off-by: Paul Collins <paul@ondioline.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc/kprobes: Some minor fixesKumar Gala2008-06-261-1/+1
| | | | | | | | | | | | | | * Mark __flush_icache_range as a function that can't be probed since its used by the kprobe code. * Fix an issue with single stepping and async exceptions. We need to ensure that we dont get an async exception (external, decrementer, etc) while we are attempting to single step the probe point. Added a check to ensure we only handle a single step if its really intended for the instruction in question. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Add IRQSTACKS support on ppc32Kumar Gala2008-04-291-0/+25
| | | | | | | | | | | | | | | | | | | | This makes it possible to use separate stacks for hard and soft IRQs on 32-bit powerpc as well as on 64-bit. The code for 32-bit is just the 32-bit analog of the 64-bit code. * Added allocation and initialization of the irq stacks. We limit the stacks to be in lowmem for ppc32. * Implemented ppc32 versions of call_do_softirq() and call_handle_irq() to switch the stack pointers * Reworked how we do stack overflow detection. We now keep around the limit of the stack in the thread_struct and compare against the limit to see if we've overflowed. We can now use this on ppc64 if desired. [ paulus@samba.org: Fixed bug on 6xx where we need to reload r9 with the thread_info pointer. ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Clean up access to thread_info in assemblyKumar Gala2008-04-241-3/+3
| | | | | | | | Use (31-THREAD_SHIFT) to get to thread_info from stack pointer. This makes the code a bit easier to read and more robust if we ever change THREAD_SHIFT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Add __ucmpdi2 for 64-bit comparisons in 32-bit kernelsPaul Mackerras2008-03-131-0/+15
| | | | | | | | | | Some drivers (such as V4L2) have code that causes gcc to generate calls to __ucmpdi2 when compiling for 32-bit powerpc, which results in either a link-time error or a module that can't be loaded, as we don't currently have a __ucmpdi2. This adds one so these drivers can be used. Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] 85xx: Only invalidate TLB0 and TLB1Kumar Gala2008-01-281-10/+0
| | | | | | | All current 85xx/e500 implementations only have two TLB arrays. We are wasting cycles by invalidating TLB2 and TLB3. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 4xx: Add early udbg support for 40x processorsBenjamin Herrenschmidt2007-12-231-0/+39
| | | | | | | | This adds some basic real mode based early udbg support for 40x in order to debug things more easily Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] kernel_execve is identical in 32 and 64 bitStephen Rothwell2007-12-111-7/+0
| | | | | | | so consolidate it into misc.S. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] 4xx: Deal with 44x virtually tagged icacheBenjamin Herrenschmidt2007-11-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | The 44x family has an interesting "feature" which is a virtually tagged instruction cache (yuck !). So far, we haven't dealt with it properly, which means we've been mostly lucky or people didn't report the problems, unless people have been running custom patches in their distro... This is an attempt at fixing it properly. I chose to do it by setting a global flag whenever we change a PTE that was previously marked executable, and flush the entire instruction cache upon return to user space when that happens. This is a bit heavy handed, but it's hard to do more fine grained flushes as the icbi instruction, on those processor, for some very strange reasons (since the cache is virtually mapped) still requires a valid TLB entry for reading in the target address space, which isn't something I want to deal with. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Fix 4xx flush_tlb_page()Benjamin Herrenschmidt2007-11-011-7/+16
| | | | | | | | | | | | | | | | | | | On 4xx CPUs, the current implementation of flush_tlb_page() uses a low level _tlbie() assembly function that only works for the current PID. Thus, invalidations caused by, for example, a COW fault triggered by get_user_pages() from a different context will not work properly, causing among other things, gdb breakpoints to fail. This patch adds a "pid" argument to _tlbie() on 4xx processors, and uses it to flush entries in the right context. FSL BookE also gets the argument but it seems they don't need it (their tlbivax form ignores the PID when invalidating according to the document I have). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] Fix small race in 44x tlbie functionDavid Gibson2007-08-151-1/+11
| | | | | | | | | | | | | | | | | | | The 440 family of processors don't have a tlbie instruction. So, we implement TLB invalidates by explicitly searching the TLB with tlbsx., then clobbering the relevant entry, if any. Unfortunately the PID for the search needs to be stored in the MMUCR register, which is also used by the TLB miss handler. Interrupts were enabled in _tlbie(), so an interrupt between loading the MMUCR and the tlbsx could cause incorrect search results, and thus a failure to invalide TLB entries which needed to be invalidated. This fixes the problem in both arch/ppc and arch/powerpc by inhibiting interrupts (even critical and debug interrupts) across the relevant instructions. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Merge CPU features pertaining to icache coherencyDavid Gibson2007-06-141-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Remove _get_SPAnton Blanchard2007-03-221-4/+0
| | | | | | | We already have an inline __get_SP, no need for yet another one. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Consolidate feature fixup codeBenjamin Herrenschmidt2006-10-251-74/+0
| | | | | | | | | | | | | | | | | There are currently two versions of the functions for applying the feature fixups, one for CPU features and one for firmware features. In addition, they are both in assembly and with separate implementations for 32 and 64 bits. identify_cpu() is also implemented in assembly and separately for 32 and 64 bits. This patch replaces them with a pair of C functions. The call sites are slightly moved on ppc64 as well to be called from C instead of from assembly, though it's a very small change, and thus shouldn't cause any problem. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [PATCH] rename the provided execve functions to kernel_execveArnd Bergmann2006-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some architectures provide an execve function that does not set errno, but instead returns the result code directly. Rename these to kernel_execve to get the right semantics there. Moreover, there is no reasone for any of these architectures to still provide __KERNEL_SYSCALLS__ or _syscallN macros, so remove these right away. [akpm@osdl.org: build fix] [bunk@stusta.de: build fix] Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Andi Kleen <ak@muc.de> Acked-by: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Richard Henderson <rth@twiddle.net> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Ian Molton <spyro@f2s.com> Cc: Mikael Starvik <starvik@axis.com> Cc: David Howells <dhowells@redhat.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Hirokazu Takata <takata.hirokazu@renesas.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Kyle McMartin <kyle@mcmartin.ca> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Kazumoto Kojima <kkojima@rr.iij4u.or.jp> Cc: Richard Curnow <rc@rc0.org.uk> Cc: William Lee Irwin III <wli@holomorphy.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jeff Dike <jdike@addtoit.com> Cc: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it> Cc: Miles Bader <uclinux-v850@lsi.nec.co.jp> Cc: Chris Zankel <chris@zankel.net> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Adrian Bunk <bunk@stusta.de> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-301-1/+0
| | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* [POWERPC] Consolidate some of kernel/misc*.SStephen Rothwell2006-06-281-156/+0
| | | | | | | | | | There were some common functions (mainly i/o). Also some small white space cleanups and remove a couple of small unused functions. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [PATCH] powerpc: remove do-nothing cpu setup routinesGeoff Levand2006-05-191-1/+1
| | | | | | | | | | | Removed the do-nothing routines __setup_cpu_power3 and __setup_cpu_power4 and replaced them with a null pointer check in the caller. Also removed the Cell processor specific routine __setup_cpu_be which improperly accessed the hypervisor page size configuration at SPR HID6. Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [PATCH] powerpc: Cleanup LOADADDR etc. asm macrosDavid Gibson2006-01-131-2/+2
| | | | | | | | | | | | | | | | | | This patch consolidates the variety of macros used for loading 32 or 64-bit constants in assembler (LOADADDR, LOADBASE, SET_REG_TO_*). The idea is to make the set of macros consistent across 32 and 64 bit and to make it more obvious which is the appropriate one to use in a given situation. The new macros and their semantics are described in the comments in ppc_asm.h. In the process, we change several places that were unnecessarily using immediate loads on ppc64 to use the GOT/TOC. Likewise we cleanup a couple of places where we were clumsily subtracting PAGE_OFFSET with asm instructions to use assemble-time arithmetic or the toreal() macro instead. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [PATCH] powerpc: Merge kexecMichael Ellerman2006-01-091-0/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch merges, to some extent, the PPC32 and PPC64 kexec implementations. We adopt the PPC32 approach of having ppc_md callbacks for the kexec functions. The current PPC64 implementation becomes the "default" implementation for PPC64 which platforms can select if they need no special treatment. I've added these default callbacks to pseries/maple/cell/powermac, this means iSeries no longer supports kexec - but it never worked anyway. I've renamed PPC32's machine_kexec_simple to default_machine_kexec, inline with PPC64. Judging by the comments it might be better named machine_kexec_non_of, or something, but at the moment it's the only implementation for PPC32 so it's the "default". Kexec requires machine_shutdown(), which is in machine_kexec.c on PPC32, but we already have in setup-common.c on powerpc. All this does is call ppc_md.nvram_sync, which only powermac implements, so instead make machine_shutdown a ppc_md member and have it call core99_nvram_sync directly on powermac. I've also stuck relocate_kernel.S into misc_32.S for powerpc. Built for ARCH=ppc, and 32 & 64 bit ARCH=powerpc, with KEXEC=y/n. Booted on P5 LPAR and successfully kexec'ed. Should apply on top of 493f25ef4087395891c99fcfe2c72e62e293e89f. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc: Fix delay functions for 601 processorsPaul Mackerras2005-11-181-8/+0
| | | | | | | | | | | My earlier merge of delay.h introduced a timebase-based udelay for 32-bit machines but also broke the 601, which doesn't have the timebase register. This fixes it by using the 601's RTC register on the 601, and also moves __delay() and udelay() to be out-of-line in arch/powerpc/kernel/time.c. These functions aren't really performance critical, after all. Signed-off-by: Paul Mackerras <paulus@samba.org>
* [PATCH] powerpc: Merge cacheflush.h and cache.hDavid Gibson2005-11-101-22/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ppc32 and ppc64 versions of cacheflush.h were almost identical. The two versions of cache.h are fairly similar, except for a bunch of register definitions in the ppc32 version which probably belong better elsewhere. This patch, therefore, merges both headers. Notable points: - there are several functions in cacheflush.h which exist only on ppc32 or only on ppc64. These are handled by #ifdef for now, but these should probably be consolidated, along with the actual code behind them later. - Confusingly, both ppc32 and ppc64 have a flush_dcache_range(), but they're subtly different: it uses dcbf on ppc32 and dcbst on ppc64, ppc64 has a flush_inval_dcache_range() which uses dcbf. These too should be merged and consolidated later. - Also flush_dcache_range() was defined in cacheflush.h on ppc64, and in cache.h on ppc32. In the merged version it's in cacheflush.h - On ppc32 flush_icache_range() is a normal function from misc.S. On ppc64, it was wrapper, testing a feature bit before calling __flush_icache_range() which does the actual flush. This patch takes the ppc64 approach, which amounts to no change on ppc32, since CPU_FTR_COHERENT_ICACHE will never be set there, but does mean renaming flush_icache_range() to __flush_icache_range() in arch/ppc/kernel/misc.S and arch/powerpc/kernel/misc_32.S - The PReP register info from asm-ppc/cache.h has moved to arch/ppc/platforms/prep_setup.c - The 8xx register info from asm-ppc/cache.h has moved to a new asm-powerpc/reg_8xx.h, included from reg.h - flush_dcache_all() was defined on ppc32 (only), but was never called (although it was exported). Thus this patch removes it from cacheflush.h and from ARCH=powerpc (misc_32.S) entirely. It's left in ARCH=ppc for now, with the prototype moved to ppc_ksyms.c. Built for Walnut (ARCH=ppc), 32-bit multiplatform (pmac, CHRP and PReP ARCH=ppc, pmac and CHRP ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built for 32-bit powermac (ARCH=ppc and ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built and booted on G5 (ARCH=powerpc) Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [PATCH] powerpc: Fix handling of fpscr on 64-bitDavid Gibson2005-10-271-27/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recent merge of fpu.S broken the handling of fpscr for ARCH=powerpc and CONFIG_PPC64=y. FP registers could be corrupted, leading to strange random application crashes. The confusion arises, because the thread_struct has (and requires) a 64-bit area to save the fpscr, because we use load/store double instructions to get it in to/out of the FPU. However, only the low 32-bits are actually used, so we want to treat it as a 32-bit quantity when manipulating its bits to avoid extra load/stores on 32-bit. This patch replaces the current definition with a structure of two 32-bit quantities (pad and val), to clarify things as much as is possible. The 'val' field is used when manipulating bits, the structure itself is used when obtaining the address for loading/unloading the value from the FPU. While we're at it, consolidate the 4 (!) almost identical versions of cvt_fd() and cvt_df() (arch/ppc/kernel/misc.S, arch/ppc64/kernel/misc.S, arch/powerpc/kernel/misc_32.S, arch/powerpc/kernel/misc_64.S) into a single version in fpu.S. The new version takes a pointer to thread_struct and applies the correct offset itself, rather than a pointer to the fpscr field itself, again to avoid confusion as to which is the correct field to use. Finally, this patch makes ARCH=ppc64 also use the consolidated fpu.S code, which it previously did not. Built for G5 (ARCH=ppc64 and ARCH=powerpc), 32-bit powermac (ARCH=ppc and ARCH=powerpc) and Walnut (ARCH=ppc, CONFIG_MATH_EMULATION=y). Booted on G5 (ARCH=powerpc) and things which previously fell over no longer do. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc: Merge time.c and asm/time.h.Paul Mackerras2005-10-201-0/+27
| | | | | | | | | | We now use the merged time.c for both 32-bit and 64-bit compilation with ARCH=powerpc, and for ARCH=ppc64, but not for ARCH=ppc32. This removes setup_default_decr (folds its function into time_init) and moves wakeup_decrementer into time.c. This also makes an asm-powerpc/rtc.h. Signed-off-by: Paul Mackerras <paulus@samba.org>
* ppc32: use L1_CACHE_SHIFT/L1_CACHE_BYTESStephen Rothwell2005-10-171-29/+29
| | | | | | instead of L1_CACHE_LINE_SIZE and LG_L1_CACHE_LINE_SIZE Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
* powerpc: create 32 bit LOADADDR macroStephen Rothwell2005-10-131-4/+2
| | | | | | and use it in misc_32.S Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
* powerpc: Introduce entry_{32,64}.S, misc_{32,64}.S, systbl.SPaul Mackerras2005-10-101-0/+1039
The system call table has been consolidated into systbl.S. We have separate 32-bit and 64-bit versions of entry.S and misc.S since the code is mostly sufficiently different to be not worth merging. There are some common bits that will be extracted in future. Signed-off-by: Paul Mackerras <paulus@samba.org>
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