Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | RISC-V: Always compile mm/init.c with cmodel=medany and notrace | Anup Patel | 2019-03-26 | 1 | -3/+0 |
* | Allow to disable FPU support | Alan Kao | 2018-10-22 | 1 | -1/+1 |
* | Extract FPU context operations from entry.S | Alan Kao | 2018-10-22 | 1 | -0/+1 |
* | perf: riscv: preliminary RISC-V support | Alan Kao | 2018-06-04 | 1 | -0/+2 |
* | RISC-V: Fixes to module loading | Palmer Dabbelt | 2018-04-02 | 1 | -0/+1 |
|\ | |||||
| * | RISC-V: Add sections of PLT and GOT for kernel module | Zong Li | 2018-04-02 | 1 | -0/+1 |
* | | riscv/ftrace: Add dynamic function tracer support | Alan Kao | 2018-04-02 | 1 | -2/+3 |
|/ | |||||
* | riscv/ftrace: Add basic support | Alan Kao | 2018-01-30 | 1 | -0/+7 |
* | RISC-V: Build Infrastructure | Palmer Dabbelt | 2017-09-26 | 1 | -0/+33 |