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* Merge branch 'next/nommu' into for-nextPaul Walmsley2019-11-221-31/+54
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| * riscv: add nommu supportChristoph Hellwig2019-11-171-0/+11
| * riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig2019-11-051-31/+43
* | riscv: add support for SECCOMP and SECCOMP_FILTERDavid Abdurachmanov2019-10-291-2/+25
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* RISC-V: entry: Remove unneeded need_resched() loopValentin Schneider2019-10-091-2/+1
* RISC-V: Clear load reservations while restoring hart contextsPalmer Dabbelt2019-10-011-1/+20
* riscv: Avoid interrupts being erroneously enabled in handle_exception()Vincent Chen2019-09-201-1/+5
* riscv: Using CSR numbers to access CSRsBin Meng2019-08-301-3/+3
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* RISC-V: Access CSRs using CSR numbersAnup Patel2019-05-161-11/+11
* RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=yVincent Chen2019-01-231-1/+17
* riscv: add audit supportDavid Abdurachmanov2019-01-071-2/+2
* RISC-V: SMP cleanup and new featuresPalmer Dabbelt2018-10-221-1/+0
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| * RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel2018-10-221-1/+0
* | Extract FPU context operations from entry.SAlan Kao2018-10-221-87/+0
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* RISC-V: implement low-level interrupt handlingChristoph Hellwig2018-08-131-2/+2
* RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handlerPalmer Dabbelt2018-03-141-4/+3
* RISC-V: Enable IRQ during exception handlingzongbox@gmail.com2018-02-201-2/+3
* riscv: disable SUM in the exception handlerChristoph Hellwig2018-01-301-3/+6
* riscv: rename SR_* constants to match the specChristoph Hellwig2018-01-071-4/+4
* RISC-V: Task implementationPalmer Dabbelt2017-09-261-0/+464
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