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* riscv: rename SR_* constants to match the specChristoph Hellwig2018-01-076-17/+17
* riscv: remove CONFIG_MMU ifdefsChristoph Hellwig2018-01-074-24/+0
* RISC-V: Make __NR_riscv_flush_icache visible to userspacePalmer Dabbelt2018-01-075-30/+27
* RISC-V: Add a basic defconfigKarsten Merker2018-01-071-0/+75
* RISC-V: Remove unused CONFIG_HVC_RISCV_SBI codePalmer Dabbelt2017-12-111-11/+0
* RISC-V: Resurrect smp_mb__after_spinlock()Palmer Dabbelt2017-12-111-0/+19
* RISC-V: Logical vs Bitwise typoDan Carpenter2017-12-111-1/+1
* bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program typeHendrik Brueckner2017-12-051-0/+1
* RISC-V: Fixes for clean allmodconfig buildPalmer Dabbelt2017-12-0112-21/+39
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| * RISC-V: Add missing includeOlof Johansson2017-11-301-0/+1
| * RISC-V: Use define for get_cycles like other architecturesOlof Johansson2017-11-301-1/+2
| * RISC-V: Provide stub of setup_profiling_timer()Olof Johansson2017-11-301-0/+7
| * RISC-V: Export some expected symbols for modulesOlof Johansson2017-11-303-0/+6
| * RISC-V: move empty_zero_page definition to C and export itOlof Johansson2017-11-302-3/+3
| * RISC-V: io.h: type fixes for warningsOlof Johansson2017-11-302-8/+10
| * RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macrosOlof Johansson2017-11-302-9/+9
| * RISC-V: use generic serial.hOlof Johansson2017-11-301-0/+1
* | RISC-V: __io_writes should respect the length argumentPalmer Dabbelt2017-12-011-1/+1
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| * | RISC-V: __io_writes should respect the length argumentPalmer Dabbelt2017-12-011-1/+1
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* | RISC-V: User-Visible ChangesPalmer Dabbelt2017-12-0119-34/+392
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| * | RISC-V: Clean up an unused includePalmer Dabbelt2017-11-301-1/+0
| * | RISC-V: Allow userspace to flush the instruction cacheAndrew Waterman2017-11-308-0/+105
| * | RISC-V: Flush I$ when making a dirty page executableAndrew Waterman2017-11-308-30/+174
| * | RISC-V: Add VDSO entries for clock_get/gettimeofday/getcpuAndrew Waterman2017-11-276-1/+113
| * | RISC-V: Remove __vdso_cmpxchg{32,64} symbol versionsPalmer Dabbelt2017-11-271-2/+0
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* | RISC-V: remove spin_unlock_wait()Palmer Dabbelt2017-11-281-9/+0
* | RISC-V: `sfence.vma` orderes the instruction cachePalmer Dabbelt2017-11-281-1/+4
* | RISC-V: Add READ_ONCE in arch_spin_is_locked()Palmer Dabbelt2017-11-281-1/+1
* | RISC-V: __test_and_op_bit_ord should be strongly orderedPalmer Dabbelt2017-11-281-1/+1
* | RISC-V: Remove smb_mb__{before,after}_spinlock()Palmer Dabbelt2017-11-281-8/+0
* | RISC-V: Remove __smp_bp__{before,after}_atomicPalmer Dabbelt2017-11-281-15/+0
* | RISC-V: Comment on why {,cmp}xchg is ordered how it isPalmer Dabbelt2017-11-281-2/+7
* | RISC-V: Remove unused arguments from ATOMIC_OPPalmer Dabbelt2017-11-281-47/+47
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* Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub...Linus Torvalds2017-11-151-14/+0
* RISC-V: Build InfrastructurePalmer Dabbelt2017-09-269-0/+579
* RISC-V: User-facing APIPalmer Dabbelt2017-09-2627-0/+1687
* RISC-V: Paging and MMUPalmer Dabbelt2017-09-268-0/+1192
* RISC-V: Device, timer, IRQs, and the SBIPalmer Dabbelt2017-09-269-0/+566
* RISC-V: Task implementationPalmer Dabbelt2017-09-269-0/+1243
* RISC-V: ELF and module implementationPalmer Dabbelt2017-09-264-0/+187
* RISC-V: Generic library routines and assemblyPalmer Dabbelt2017-09-2611-0/+1389
* RISC-V: Atomic and Locking CodePalmer Dabbelt2017-09-2610-0/+1423
* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-2615-0/+1524
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