summaryrefslogtreecommitdiffstats
path: root/arch/riscv
Commit message (Expand)AuthorAgeFilesLines
...
| * | RISC-V: Allow userspace to flush the instruction cacheAndrew Waterman2017-11-308-0/+105
| * | RISC-V: Flush I$ when making a dirty page executableAndrew Waterman2017-11-308-30/+174
| * | RISC-V: Add VDSO entries for clock_get/gettimeofday/getcpuAndrew Waterman2017-11-276-1/+113
| * | RISC-V: Remove __vdso_cmpxchg{32,64} symbol versionsPalmer Dabbelt2017-11-271-2/+0
| |/
* | RISC-V: remove spin_unlock_wait()Palmer Dabbelt2017-11-281-9/+0
* | RISC-V: `sfence.vma` orderes the instruction cachePalmer Dabbelt2017-11-281-1/+4
* | RISC-V: Add READ_ONCE in arch_spin_is_locked()Palmer Dabbelt2017-11-281-1/+1
* | RISC-V: __test_and_op_bit_ord should be strongly orderedPalmer Dabbelt2017-11-281-1/+1
* | RISC-V: Remove smb_mb__{before,after}_spinlock()Palmer Dabbelt2017-11-281-8/+0
* | RISC-V: Remove __smp_bp__{before,after}_atomicPalmer Dabbelt2017-11-281-15/+0
* | RISC-V: Comment on why {,cmp}xchg is ordered how it isPalmer Dabbelt2017-11-281-2/+7
* | RISC-V: Remove unused arguments from ATOMIC_OPPalmer Dabbelt2017-11-281-47/+47
|/
* Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub...Linus Torvalds2017-11-151-14/+0
* RISC-V: Build InfrastructurePalmer Dabbelt2017-09-269-0/+579
* RISC-V: User-facing APIPalmer Dabbelt2017-09-2627-0/+1687
* RISC-V: Paging and MMUPalmer Dabbelt2017-09-268-0/+1192
* RISC-V: Device, timer, IRQs, and the SBIPalmer Dabbelt2017-09-269-0/+566
* RISC-V: Task implementationPalmer Dabbelt2017-09-269-0/+1243
* RISC-V: ELF and module implementationPalmer Dabbelt2017-09-264-0/+187
* RISC-V: Generic library routines and assemblyPalmer Dabbelt2017-09-2611-0/+1389
* RISC-V: Atomic and Locking CodePalmer Dabbelt2017-09-2610-0/+1423
* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-2615-0/+1524
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-16 03:17:26 +0000