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* Consolidate PTRACE_DETACHAlexey Dobriyan2007-10-161-4/+0
| | | | | | | | | | | Identical handlers of PTRACE_DETACH go into ptrace_request(). Not touching compat code. Not touching archs that don't call ptrace_request. Signed-off-by: Alexey Dobriyan <adobriyan@sw.ru> Acked-by: Christoph Hellwig <hch@infradead.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6Linus Torvalds2007-10-1343-1198/+2691
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (124 commits) sh: allow building for both r2d boards in same binary. sh: fix r2d board detection sh: Discard .exit.text/.exit.data at runtime. sh: Fix up some section alignments in linker script. sh: Fix SH-4 DMAC CHCR masking. sh: Rip out left-over nommu cond syscall cruft. sh: Make kgdb i-cache flushing less inept. sh: kgdb section mismatches and tidying. sh: cleanup struct irqaction initializers. sh: early_printk tidying. video: pvr2fb: Add TV (RGB) support to Dreamcast PVR driver. sh: Conditionalize gUSA support. sh: Follow gUSA preempt changes in __switch_to(). sh: Tidy up gUSA preempt handling. sh: __copy_user() optimizations for small copies. sh: clkfwk: Support multi-level clock propagation. sh: Fix URAM start address on SH7785. sh: Use boot_cpu_data for CPU probe. sh: Support extended mode TLB on SH-X3. sh: Bump MAX_ACTIVE_REGIONS for SH7785. ...
| * sh: Discard .exit.text/.exit.data at runtime.Paul Mundt2007-10-091-0/+5
| | | | | | | | | | | | | | These were previously discarded at link time, though as with MIPS we keep them around until runtime to satisfy .rodata references. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Fix up some section alignments in linker script.Paul Mundt2007-10-091-0/+4
| | | | | | | | | | | | | | | | With the PERCPU() macro introduction .data.cacheline_aligned was inhereting PAGE_SIZE alignment, fix that up for L1_CACHE_BYTES again. Likewise, the initramfs section wants PAGE_SIZE alignment. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Rip out left-over nommu cond syscall cruft.Paul Mundt2007-10-041-18/+0
| | | | | | | | | | | | | | | | | | At some point way back when (2.5 or so) quite a few syscalls hadn't yet been wired up as cond_syscalls(), so we opted to just do direct sys_ni_syscall wrapping in the assembly code instead. That's all been fixed up since then, so we can drop the wrapping. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Make kgdb i-cache flushing less inept.Paul Mundt2007-10-031-4/+4
| | | | | | | | | | | | | | | | | | | | | | kgdb had its own ranged I-cache flushing routine that attempted to duplicate the flush_icache_range() functionality, but managed to do an explicit D-cache writeback & invalidate twice on SH-4. This is a no-op for SH-3, and the flush_icache_range() semantics already do what kgdb was feebly attempting to do already, so just move over to that and kill off the wrapper. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: kgdb section mismatches and tidying.Paul Mundt2007-10-031-42/+3
| | | | | | | | | | | | | | | | | | The kgdb console setup was callable from a left-over deferred initialization path, which in turn depends on __init symbols. Since the deferred initialization was removed some time ago, kill off the rest of those remnants and move kgdb_init() and friends to __init. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: early_printk tidying.Paul Mundt2007-10-021-11/+4
| | | | | | | | | | | | | | | | setup_early_printk() can be static, and with that, we can kill off the early initialization variable and move the CON_BOOT check in to the function body. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Conditionalize gUSA support.Paul Mundt2007-09-283-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This conditionalizes gUSA support. gUSA is not supported on SMP configurations, and it's not necessary there anyways due to having other atomicity options (ie, movli.l/movco.l). Anything implementing the LL/SC semantics (all SH-4A CPUs) can switch to userspace atomicity implementations without requiring gUSA. This is left default-enabled on all UP so that glibc doesn't break. Those that know what they are doing can disable this explicitly. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Follow gUSA preempt changes in __switch_to().Paul Mundt2007-09-281-3/+3
| | | | | | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Tidy up gUSA preempt handling.Paul Mundt2007-09-281-7/+3
| | | | | | | | | | | | | | | | Currently gUSA toggles hardirqs to disable preemption in the signal handler. Make the preemption toggling explicit, and kill off some CONFIG_PREEMPT ifdefs in the process. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: clkfwk: Support multi-level clock propagation.Stuart Menefy2007-09-281-0/+2
| | | | | | | | | | | | | | | | Currently clock propagation only works for one level, but we have some clocks which need to propagate multiple levels, so make this recursive. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Fix URAM start address on SH7785.Paul Mundt2007-09-271-1/+1
| | | | | | | | | | | | | | | | Not all of the SH-X2 URAM blocks are mapped in the same place, SH7785 happens to map it on the opposite end of the address space from SH7722, correct the addresses. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Use boot_cpu_data for CPU probe.Paul Mundt2007-09-274-129/+126
| | | | | | | | | | | | | | | | | | | | This moves off of smp_processor_id() and only sets the probe information for the boot CPU directly. This will be copied out for the secondaries, so there's no reason to do this each time. This also allows for some header tidying. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Fix plat_irq_setup_pins() for SH7785.Paul Mundt2007-09-271-4/+0
| | | | | | | | | | | | | | There was some debug code left in here that caused the pin changes to never be hit. Kill that off, and all is well. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Disable L2 reporting for present URAM only parts.Paul Mundt2007-09-271-5/+2
| | | | | | | | | | | | | | | | | | The probing logic works for both URAM and L2, with no way to distinguish between the two. Disable the probing for now and let the CPU subtypes that have this in a real L2 configuration explicitly say so. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Define _ebss for uClinux MTD map driver.Paul Mundt2007-09-242-1/+3
| | | | | | | | | | | | | | The uClinux MTD device uses _ebss, add the symbol and corresponding export. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Initial SH-X3 SMP support.Paul Mundt2007-09-212-1/+125
| | | | | | | | | | | | | | | | | | | | | | This adds basic support for SH-X3 SMP (4 CPUs). More IPI and cache debugging is necessary, mostly interfacing the d-cache coherency and the I-cache broadcast invalidates. Only for testing at present! Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Plug plat_smp_setup() in to generic setup path.Paul Mundt2007-09-211-0/+5
| | | | | | | | | | | | | | Now that the SMP stubs are in place, call in to the setup code to be defined by the platform. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Hook up the SH-X3 SMP intc register groups.Magnus Damm2007-09-211-1/+1
| | | | | | | | | | Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Bring SMP support back from the dead.Paul Mundt2007-09-214-88/+118
| | | | | | | | | | | | | | | | | | | | | | There was a very preliminary bunch of SMP code scattered around for the SH7604 microcontrollers from way back when, and it has mostly suffered bitrot since then. With the tree already having been slowly getting prepped for SMP, this plugs in most of the remaining platform-independent bits. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc - initial SMP support.Magnus Damm2007-09-211-21/+57
| | | | | | | | | | | | | | | | | | | | | | | | This implements initial support for the SMP INTC (particularly INTC2) controllers. These are largely implemented as conventional blocks, with register sets grouped together at fixed strides relative to the CPU id. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Add SMP tlbflush variants.Paul Mundt2007-09-211-0/+140
| | | | | | | | | | | | | | | | This adds the TLB flushing routines for SMP systems, based on the MIPS implementation, with some additional SH-specific flush routines. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Kill off special boot_cpu_data.Paul Mundt2007-09-212-2/+7
| | | | | | | | | | | | | | | | This consolidates the cpu_data definitions and gets rid of the special boot_cpu_data. It's made a wrapper to the boot CPU, in order to keep the existing in-tree users happy. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Make cpufreq driver less noisy on SMP.Paul Mundt2007-09-211-2/+1
| | | | | | | | | | | | | | The cpufreq driver banner is currently printed for each CPU, move it down so it's not as noisy and it's only printed once. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Wire up URAM node on SH7785.Paul Mundt2007-09-211-0/+8
| | | | | | | | | | | | Add SH7785 URAM as node 1, follows the SH-X3 change. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: INTC stubs for SH7343 and SH7770 builds.Paul Mundt2007-09-212-0/+8
| | | | | | | | | | | | | | Get the SH7343 and SH7770 stuff linking again. Both of these still require proper INTC support. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc - irl mode update for sh7780 and sh7785Magnus Damm2007-09-212-4/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains the following fixes and improvements: - Fix address typo for INTMSK2 / INTMSKCLR2 registers on sh7780. - Adds IRQ_MODE_IRLnnnn_MASK using intc controller for IRL masking. - Good old IRQ_MODE_IRLnnnn should not register any intc controller. - plat_irq_setup_pins() now selects IRL or IRQ mode. - the holding function is now disabled using ICR0. By default all external pin interrupts are disabled. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: remove CONFIG_CPU_HAS_INTC_IRQMagnus Damm2007-09-211-2/+1
| | | | | | | | | | | | | | | | | | All processor specific interrupt code is now converted to make use of the new intc code. The config option CONFIG_CPU_HAS_INTC_IRQ is because of that pointless. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Kill off volatile silliness in sq_flush_range().Paul Mundt2007-09-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | CC arch/sh/kernel/cpu/sh4/sq.o arch/sh/kernel/cpu/sh4/sq.c: In function 'sq_flush_range': arch/sh/kernel/cpu/sh4/sq.c:65: warning: passing argument 1 of 'prefetch' discards qualifiers from pointer target type This didn't actually need to be volatile in the first place, so just kill off the qualifier entirely. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc - add support for sh7206Magnus Damm2007-09-211-51/+158
| | | | | | | | | | | | | | | | | | This patch converts the cpu specific interrupt setup code for sh7206 from ipr to intc. New vectors are also added to match the information provided by the datasheet. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc - add support for sh7619Magnus Damm2007-09-211-37/+56
| | | | | | | | | | | | | | | | | | This patch converts the cpu specific interrupt setup code for sh7619 from ipr to intc. New vectors are also added to match the information provided by the datasheet. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: fix irqs for the second serial port on sh7206Magnus Damm2007-09-211-4/+4
| | | | | | | | | | | | | | | | | | This patch makes sure the serial port interrupt irqs matches the datasheet. Only irqs for SCIF1 are changed. While at some cosmetic spaces are added. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc - primary priority masking fixesMagnus Damm2007-09-211-5/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains various intc fixes for problems reported by Markus Brunner on the linuxsh-dev mailing list: http://marc.info/?l=linuxsh-dev&m=118701948224991&w=1 Apart from added comments, the fixes are: - add intc_set_priority() function prototype to hw_irq.h - fix off-by-one error in intc_set_priority() - make sure _INTC_WIDTH() is set for primary priority masking Big thanks to Markus for finding these problems. Version two fixes a compile error and an inverted primary check. Signed-off-by: Magnus Damm <damm@igel.co.jp> Acked-by: Markus Brunner <super.firetwister@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc - mark data structures as __initdataMagnus Damm2007-09-219-71/+70
| | | | | | | | | | | | | | | | | | | | | | With the intc core improved it is now possible to put the intc data structures in the initdata section. Version two of this patch puts the __initdata inside DECLARE_INTC_DESC() and removes the __initdata included in the board specific r2d code. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: x3 - add ipi vectorsMagnus Damm2007-09-211-0/+9
| | | | | | | | | | | | | | | | With the intc dual prio register support in place it is now possible to add the ipi vectors to x3. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc - rework core codeMagnus Damm2007-09-211-211/+327
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reworks the intc core, implementing the following features: - Support dual priority registers - one set and one clear register - All 8/16/32 bit register combinations are now supported - Both single mask and single enable bitmap register are supported - Add code to set interrupt priority - Speedup sense and priority configuration code - Allocate data using bootmem, allows intc data structures to be __initdata - Save memory - allocated memory footprint is smaller than intc structures Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc - add a clear register to struct intc_prio_regMagnus Damm2007-09-2110-96/+104
| | | | | | | | | | | | | | | | We need a secondary register member in struct intc_prio_reg to support dual priority registers used by ipi on x3. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: x3 - fix setup_bootmem_node() compile error with shx3_defconfigMagnus Damm2007-09-211-0/+1
| | | | | | | | | | | | | | | | | | This makes sure the function prototype for setup_bootmem_node() gets included. The file setup-shx3.c does not compile otherwise for CONFIG_NUMA=n. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Add SH7720 CPU support.Markus Brunner2007-09-216-6/+252
| | | | | | | | | | | | | | | | This adds support for the SH7720 (SH3-DSP) CPU. Signed-off by: Markus Brunner <super.firetwister@gmail.com> Signed-off by: Mark Jonas <toertel@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Kill off duplicate symbol exports on SMP.Paul Mundt2007-09-211-6/+1
| | | | | | | | | | | | | | synchronize_irq() was being exported twice, kill off the duplicate export. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Wire up CSM node for SH-X3.Paul Mundt2007-09-211-5/+8
| | | | | | | | | | | | | | Now that NODES_SHIFT is bumped up, we can plug in the CSM block as a separate node, too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc: Fix sense regs oops for IRL IRQs.Paul Mundt2007-09-211-1/+1
| | | | | | | | | | | | | | | | IRL doesn't always define sense registers, so don't bother trying to iterate through the table. This ended up causing an oops on SH-X3 when using IRL mode. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: remove intc2 codeMagnus Damm2007-09-212-87/+0
| | | | | | | | | | | | | | There is no point in keeping around the now unused intc2 code. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc - add single bitmap register supportMagnus Damm2007-09-211-11/+62
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds single bitmap register support to intc. The current code only handles 16 and 32 bit registers where a set bit means interrupt enabled, but this is easy to extend in the future. The INTC_IRQ() macro is also added to provide a way to hook in interrupt controllers for FPGAs in boards or companion chips. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc - remove redundant irq code for shminMagnus Damm2007-09-211-0/+4
| | | | | | | | | | | | | | | | | | This patch removes redundant interrupt code for the shmin board which is using a sh770x processor and 4 IRQ lines as individual interrupts (IRQ-mode). Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc - remove redundant irq code for sh03, snapgear and titanMagnus Damm2007-09-211-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes redundant board specific interrupt code for boards using sh775x processors and 4 IRQ lines in "Individual Interrupt Mode" aka IRLM. Three boards are affected: sh03, snapgear and titan. The right way to do this is to use cpu specific code provided by intc. A nice side effect is that sh03 now compiles, board not BROKEN any more. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * rtc: rtc-sh: Support 4-digit year on SH7705/SH7710/SH7712.Paul Mundt2007-09-212-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All SH-4 parts have a 4-digit year, while the SH-3 parts typically only use a 2-digit one. The SH7705, SH7710, and SH7712 SH-3 parts however opted to extend it to 4-digit and still look and act like an SH-3 RTC in all other ways. This adds a capability flag (RTC_CAP_4_DIGIT_YEAR) that these corner-case CPU subtypes can set in their platform data and cleans up some of the ifdef mess in the driver as a result. Reported-by: Markus Brunner <super.firetwister@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Initial multiple-node support for SH-X3.Paul Mundt2007-09-211-0/+14
| | | | | | | | | | | | Wire up CPU#0 URAM as node 1 on SH-X3. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: intc - add support for x3Magnus Damm2007-09-211-16/+188
| | | | | | | | | | | | | | | | | | | | | | This patch converts the cpu specific interrupt setup code for x3 from intc2 to intc. New vectors are also added to match the preliminary information. Use plat_irq_setup_pins() to select between IRQ and IRL mode for IRQ0-3. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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