summaryrefslogtreecommitdiffstats
path: root/arch/sh/mm/tlb-sh4.c
Commit message (Collapse)AuthorAgeFilesLines
* sh: Fix up the SH-3 build for recent TLB changes.Paul Mundt2010-04-021-0/+28
| | | | | | | | | | | | While the MMUCR.URB and ITLB/UTLB differentiation works fine for all SH-4 and later TLBs, these features are absent on SH-3. This splits out local_flush_tlb_all() in to SH-4 and PTEAEX copies while restoring the old SH-3 one, subsequently fixing up the build. This will probably want some further reordering and tidying in the future, but that's out of scope at present. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Mass ctrl_in/outX to __raw_read/writeX conversion.Paul Mundt2010-01-261-5/+5
| | | | | | | | | | | The old ctrl in/out routines are non-portable and unsuitable for cross-platform use. While drivers/sh has already been sanitized, there is still quite a lot of code that is not. This converts the arch/sh/ bits over, which permits us to flag the routines as deprecated whilst still building with -Werror for the architecture code, and to ensure that future users are not added. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Kill off the special uncached section and fixmap.Paul Mundt2010-01-211-2/+1
| | | | | | | | Now that cached_to_uncached works as advertized in 32-bit mode and we're never going to be able to map < 16MB anyways, there's no need for the special uncached section. Kill it off. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Split out MMUCR.URB based entry wiring in to shared helper.Paul Mundt2010-01-191-66/+0
| | | | | | | | | | | Presently this is duplicated between tlb-sh4 and tlb-pteaex. Split the helpers out in to a generic tlb-urb that can be used by any parts equipped with MMUCR.URB. At the same time, move the SH-5 code out-of-line, as we require single global state for DTLB entry wiring. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: New extended page flag to wire/unwire TLB entriesMatt Fleming2010-01-161-0/+66
| | | | | | | | Provide a new extended page flag, _PAGE_WIRED and an SH4 implementation for wiring TLB entries and use it in the fixmap code path so that we can wire the fixmap TLB entry. Signed-off-by: Matt Fleming <matt@console-pimps.org>
* Merge branch 'master' into sh/smpPaul Mundt2009-09-011-3/+6
|\ | | | | | | | | Conflicts: arch/sh/mm/cache-sh4.c
| * sh: Better description of SH-4 PTEA register update.Michael Trimarchi2009-08-201-3/+6
| | | | | | | | | | Signed-off-by: Michael Trimarchi <trimarchimichael@yahoo.it> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: Handle a NULL vma in __update_tlb() for the fast-path.Paul Mundt2009-07-291-1/+1
| | | | | | | | | | | | | | | | The TLB miss fast-path presently calls in to update_mmu_cache() to set up the entry, and does so with a NULL vma. Check for vma validity in the __update_tlb() ptrace checks. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: update_mmu_cache() consolidation.Paul Mundt2009-07-291-23/+6
| | | | | | | | | | | | | | | | | | This splits out a separate __update_cache()/__update_tlb() for update_mmu_cache() to wrap in to. This lets us share the common __update_cache() bits while keeping special __update_tlb() handling broken out. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: Migrate from PG_mapped to PG_dcache_dirty.Paul Mundt2009-07-221-12/+11
|/ | | | | | | | | | | | | | | | | This inverts the delayed dcache flush a bit to be more in line with other platforms. At the same time this also gives us the ability to do some more optimizations and cleanup. Now that the update_mmu_cache() callsite only tests for the bit, the implementation can gradually be split out and made generic, rather than relying on special implementations for each of the peculiar CPU types. SH7705 in 32kB mode and SH-4 still need slightly different handling, but this is something that can remain isolated in the varying page copy/clear routines. On top of that, SH-X3 is dcache coherent, so there is no need to bother with any of these tests in the PTEAEX version of update_mmu_cache(), so we kill that off too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Preparation for uncached jumps through PMB.Stuart Menefy2008-01-281-3/+4
| | | | | | | | | | | | Presently most of the 29-bit physical parts do P1/P2 segmentation with a 1:1 cached/uncached mapping, jumping between the two to control the caching behaviour. This provides the basic infrastructure to maintain this behaviour on 32-bit physical parts that don't map P1/P2 at all, using a shiny new linker section and corresponding fixmap entry. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix up extended mode TLB for SH-X2+ cores.Paul Mundt2007-09-211-17/+13
| | | | | | | | | | | | | | | | The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot, correspondingly, the PGD also has to be 64-bits, so fix that up. The kernel and user permission bits really are decoupled in early cuts of the silicon, which means that we also have to set corresponding kernel permissions on user pages or we end up with user pages that the kernel simply can't touch (!). Finally, with those things corrected, really enable MMUCR.ME and correct the PTEA value (this simply needs to be the upper 32-bits of the PTE, with the size and protection bit encoding). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Support explicit L1 cache disabling.Paul Mundt2007-09-211-10/+15
| | | | | | | | | This reworks the cache mode configuration in Kconfig, and allows for explicit selection of write-back/write-through/off configurations. All of the cache flushing routines are optimized away for the off case. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Revert lazy dcache writeback changes.Paul Mundt2007-03-051-1/+67
| | | | | | | These ended up causing too many problems on older parts, revert for now.. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Local TLB flushing variants for SMP prep.Paul Mundt2007-02-131-1/+1
| | | | | | | Rename the existing flush routines to local_ variants for use by the IPI-backed global flush routines on SMP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Lazy dcache writeback optimizations.Paul Mundt2007-02-131-67/+1
| | | | | | | | | | | | | | | This converts the lazy dcache handling to the model described in Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a bonus, this slightly cuts down on the cache flushing frequency. With that and the PTEA handling out of the way, the update_mmu_cache() implementations can be consolidated, and we no longer have to worry about which configuration the cache is in for the SH7705 case. And finally, explicitly disable the lazy writeback on SMP (SH-4A). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add flag for MMU PTEA capability.Paul Mundt2006-09-271-8/+4
| | | | | | Add CPU_HAS_PTEA, refactor some of the cpu flag settings. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Support for SH7770/SH7780 CPU subtypes.Paul Mundt2006-09-271-0/+4
| | | | | | Merge support for SH7770 and SH7780 SH-4A subtypes. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-161-0/+96
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 10:21:52 +0000