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* sh: Kill off deprecated fixed PCI memory window accessors.Paul Mundt2010-01-291-15/+0
| | | | | | | This kills off the deprected fixed memory range accessors for the cases of non-translatable ioremapping. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Mass ctrl_in/outX to __raw_read/writeX conversion.Paul Mundt2010-01-2610-52/+52
| | | | | | | | | | | The old ctrl in/out routines are non-portable and unsuitable for cross-platform use. While drivers/sh has already been sanitized, there is still quite a lot of code that is not. This converts the arch/sh/ bits over, which permits us to flag the routines as deprecated whilst still building with -Werror for the architecture code, and to ensure that future users are not added. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Kill off the special uncached section and fixmap.Paul Mundt2010-01-217-16/+10
| | | | | | | | Now that cached_to_uncached works as advertized in 32-bit mode and we're never going to be able to map < 16MB anyways, there's no need for the special uncached section. Kill it off. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Track the uncached mapping size.Paul Mundt2010-01-211-7/+14
| | | | | | | | | This provides a variable for tracking the uncached mapping size, and uses it for pretty printing the uncached lowmem range. Beyond this, we'll also be building on top of this for figuring out from where the remainder of P2 becomes usable when constructing unrelated mappings. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: pretty print virtual memory map on boot.Paul Mundt2010-01-201-2/+36
| | | | | | | | | This cribs the pretty printing from arch/x86/mm/init_32.c to dump the virtual memory layout on boot. This is primarily intended as a debugging aid, given that the newer CPUs have full control over their address space and as such have little to nothing in common with the legacy layout. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Correct iounmap fixmap teardown.Paul Mundt2010-01-201-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | iounmap_fixed() had a couple of bugs in it that caused it to effectively fail at life. The total number of pages to unmap factored in the mapping offset and aligned up to the next page boundary, which doesn't match the ioremap_fixed() behaviour. When ioremap_fixed() pegs a slot, the address in the mapping data already contains the offset displacement, and the size is recorded verbatim given that we're only interested in total number of pages required. As such, we need to calculate the total number from the original size in the unmap path as well. At the same time, there was also an off-by-1 problem in the fixmap index calculation which has also been corrected. Previously subsequent remaps of an identical fixmap index would trigger the pte_ERROR() in set_pte_phys(): arch/sh/mm/init.c:77: bad pte 8053ffb0(0000781003fff506). arch/sh/mm/init.c:77: bad pte 8053ffb0(0000781003fff506). arch/sh/mm/init.c:77: bad pte 8053ffb0(0000781003fff506). arch/sh/mm/init.c:77: bad pte 8053ffb0(0000781003fff506). arch/sh/mm/init.c:77: bad pte 8053ffb0(0000781003fff506). arch/sh/mm/init.c:77: bad pte 8053ffb0(0000781003fff506). With this patch in place, the iounmap-driven fixmap teardown actually does what it's supposed to do. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Make 29/32-bit mode check helper generally available.Paul Mundt2010-01-202-7/+5
| | | | | | | | Presently __in_29bit_mode() is only defined for the PMB case, but it's also easily derived from the CONFIG_29BIT and CONFIG_32BIT && CONFIG_PMB=n cases. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh64: Fix up PC casting in unaligned fixup notifier with 32bit ABI.Paul Mundt2010-01-191-2/+2
| | | | | | | | | | | | | | | | | Presently the build bails with the following: CC arch/sh/mm/alignment.o cc1: warnings being treated as errors arch/sh/mm/alignment.c: In function 'unaligned_fixups_notify': arch/sh/mm/alignment.c:69: warning: cast to pointer from integer of different size arch/sh/mm/alignment.c:74: warning: cast to pointer from integer of different size make[2]: *** [arch/sh/mm/alignment.o] Error 1 This is due to the fact that regs->pc is always 64-bit, while the pointer size depends on the ABI. Wrapping through instruction_pointer() takes care of the appropriate casting for both configurations. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Kill off now bogus fixmap/page wiring documentation.Paul Mundt2010-01-191-15/+0
| | | | | | | | | The plans for _PAGE_WIRED were detailed in a comment with the fixmap code, but as it's now all taken care of, we no longer have any reason for keeping it around, particularly since it's no longer accurate. Kill it off. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Split out MMUCR.URB based entry wiring in to shared helper.Paul Mundt2010-01-195-134/+122
| | | | | | | | | | | Presently this is duplicated between tlb-sh4 and tlb-pteaex. Split the helpers out in to a generic tlb-urb that can be used by any parts equipped with MMUCR.URB. At the same time, move the SH-5 code out-of-line, as we require single global state for DTLB entry wiring. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Kill off duplicate address alignment in ioremap_fixed().Paul Mundt2010-01-192-20/+4
| | | | | | | | This is already taken care of in the top-level ioremap, and now that no one should be calling ioremap_fixed() directly we can simply throw the mapping displacement in as an additional argument. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Prevent 64-bit pgprot clobbering across ioremap implementations.Paul Mundt2010-01-191-5/+4
| | | | | | | | | | | | | Presently 'flags' gets passed around a lot between the various ioremap helpers and implementations, which is only 32-bits. In the X2TLB case we use 64-bit pgprots which presently results in the upper 32bits being chopped off (which handily include our read/write/exec permissions). As such, we convert everything internally to using pgprot_t directly and simply convert over with pgprot_val() where needed. With this in place, transparent fixmap utilization for early ioremap works as expected. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Flag __ioremap_caller() __init_refok.Paul Mundt2010-01-181-2/+3
| | | | | | | | The mem_init_done test makes sure that this path is only entered in __init cases, so leaving ioremap_fixed() as __init and flagging the caller __init_refok is sufficient. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Handle unmapping of fixed slots transparently in iounmap().Paul Mundt2010-01-181-0/+6
| | | | | | | | | iounmap() should balance whatever is done by ioremap(). Presently ioremap() can do any of fixed mappings, PMB mappings, or page table mappings. Presently only the latter two are handled through the standard unmap path, so tie in the fixed unmapping, too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Make iounmap_fixed() return success/failure for iounmap() path.Paul Mundt2010-01-181-2/+7
| | | | | | | | This converts iounmap_fixed() to return success/error if it handled the unmap request or not. At the same time, drop the __init label, as this can be called in to later. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Merge _32/_64 ioremap implementations.Paul Mundt2010-01-183-48/+1
| | | | | | | There is nothing of interest in the _64 version anymore, so the _32 one can be renamed and used unconditionally. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Handle early ioremaps through fixed mappings.Paul Mundt2010-01-182-3/+13
| | | | | | | This adds in a mem_init_done to work out when a standard ioremap() is possible, falling back to the fixmap based ioremap otherwise. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* Merge branch 'sh/ioremap-fixed'Paul Mundt2010-01-189-292/+350
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| * sh: Tidy up non-translatable checks in iounmap path.Paul Mundt2010-01-171-4/+24
| | | | | | | | | | | | | | | | This tidies up the iounmap path with consolidated checks for nontranslatable mappings. This is in preparation of unifying the implementations. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Use ioremap_fixed() to implement SH-5 ioremap()Matt Fleming2010-01-161-283/+4
| | | | | | | | | | | | | | | | Use the fixmap-based memory mapping implementation for SH-5's ioremap() functions and delete the old static allocator that was borrowed from sparc. Signed-off-by: Matt Fleming <matt@console-pimps.org>
| * sh: Add fixed ioremap supportMatt Fleming2010-01-163-0/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | Some devices need to be ioremap'd and accessed very early in the boot process. It is not possible to use the standard ioremap() function in this case because that requires kmalloc()'ing some virtual address space and kmalloc() may not be available so early in boot. This patch provides fixmap mappings that allow physical address ranges to be remapped into the kernel address space during the early boot stages. Signed-off-by: Matt Fleming <matt@console-pimps.org>
| * sh: Generalise the pte handling code for the fixmap pathMatt Fleming2010-01-161-4/+40
| | | | | | | | | | | | | | Generalise the code for setting and clearing pte's and allow TLB entries to be pinned and unpinned if the _PAGE_WIRED flag is present. Signed-off-by: Matt Fleming <matt@console-pimps.org>
| * sh: Acquire some more page flags for SH-5.Matt Fleming2010-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | We need some more page flags to hook up _PAGE_WIRED (and eventually other things). So use the unused PTE bits above the PPN field as no implementations use these for anything currently. Now that we have _PAGE_WIRED let's provide the SH-5 functions for wiring up TLB entries. Signed-off-by: Matt Fleming <matt@console-pimps.org>
| * sh: New extended page flag to wire/unwire TLB entriesMatt Fleming2010-01-162-0/+132
| | | | | | | | | | | | | | | | Provide a new extended page flag, _PAGE_WIRED and an SH4 implementation for wiring TLB entries and use it in the fixmap code path so that we can wire the fixmap TLB entry. Signed-off-by: Matt Fleming <matt@console-pimps.org>
* | sh: Setup early PMB mappings.Matt Fleming2010-01-181-51/+105
|/ | | | | | | | | | | | | | | | | | | | | | More and more boards are going to start shipping that boot with the MMU in 32BIT mode by default. Previously we relied on the bootloader to setup PMB mappings for use by the kernel but we also need to cater for boards whose bootloaders don't set them up. If CONFIG_PMB_LEGACY is not enabled we have full control over our PMB mappings and can compress our address space. Usually, the distance between the the cached and uncached mappings of RAM is always 512MB, however we can compress the distance to be the amount of RAM on the board. pmb_init() now becomes much simpler. It no longer has to calculate any mappings, it just has to synchronise the software PMB table with the hardware. Tested on SDK7786 and SH7785LCR. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Guard against early IPIs in flush_cache_all().Paul Mundt2010-01-151-2/+11
| | | | | | | | | flush_cache_all() gets called in to when we do some early ioremapping. Unfortunately on SDK7786 the interrupt controller itself requires ioremapping, leading to a bit of a chicken and egg scenario. For now, don't bother with IPI crosscalls if there aren't any other CPUs online. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: default to extended TLB support.Paul Mundt2010-01-132-32/+6
| | | | | | | | | | | | | | | All SH-X2 and SH-X3 parts support an extended TLB mode, which has been left as experimental since support was originally merged. Now that it's had some time to stabilize and get some exposure to various platforms, we can drop it as an option and default enable it across the board. This is also good future proofing for newer parts that will drop support for the legacy TLB mode completely. This will also force 3-level page tables for all newer parts, which is necessary both for the varying page sizes and larger memories. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: fixed PMB mode refactoring.Paul Mundt2010-01-133-65/+67
| | | | | | | | | | | | | | | | | | | | | | This introduces some much overdue chainsawing of the fixed PMB support. fixed PMB was introduced initially to work around the fact that dynamic PMB mode was relatively broken, though they were never intended to converge. The main areas where there are differences are whether the system is booted in 29-bit mode or 32-bit mode, and whether legacy mappings are to be preserved. Any system booting in true 32-bit mode will not care about legacy mappings, so these are roughly decoupled. Regardless of the entry point, PMB and 32BIT are directly related as far as the kernel is concerned, so we also switch back to having one select the other. With legacy mappings iterated through and applied in the initialization path it's now possible to finally merge the two implementations and permit dynamic remapping overtop of remaining entries regardless of whether boot mappings are crafted by hand or inherited from the boot loader. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Always provide thread_info allocators.Paul Mundt2010-01-121-29/+0
| | | | | | | | Presently the thread_info allocators are special cased, depending on THREAD_SHIFT < PAGE_SHIFT. This provides a sensible definition for them regardless of configuration, in preparation for extended CPU state. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Split out the unaligned counters and user bits.Paul Mundt2010-01-122-1/+160
| | | | | | | | This splits out the unaligned access counters and userspace bits in to their own generic interface, which will allow them to be wired up on sh64 too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix up nommu build for out-of-line pgtable changes.Paul Mundt2010-01-061-0/+4
| | | | | | | pgtable_cache_init() has been moved out-of-line, so we also need a dummy definition for it on nommu to fix up the build. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* Merge branch 'sh/pgtable' of git://github.com/mfleming/linux-2.6Paul Mundt2010-01-054-13/+63
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| * sh: Move page table allocation out of lineMatt Fleming2010-01-022-1/+58
| | | | | | | | | | | | | | | | | | | | We also switched away from quicklists and instead moved to slab caches. After benchmarking both implementations the difference is negligible. The slab caches suit us better though because the size of a pgd table is just 4 entries when we're using a 3-level page table layout and quicklists always deal with pages. Signed-off-by: Matt Fleming <matt@console-pimps.org>
| * sh: Optimise flush_dcache_page() on SH4Matt Fleming2010-01-021-10/+3
| | | | | | | | | | | | | | If the page is not mapped into any process's address space then aliases cannot exist in the cache. So reduce the amount of flushing we perform. Signed-off-by: Matt Fleming <matt@console-pimps.org>
| * sh: Correct the PTRS_PER_PMD and PMD_SHIFT valuesMatt Fleming2010-01-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous expressions were wrong which made free_pmd_range() explode when using anything other than 4KB pages (which is why 8KB and 64KB pages were disabled with the 3-level page table layout). The problem was that pmd_offset() was returning an index of non-zero when it should have been returning 0. This non-zero offset was used to calculate the address of the pmd table to free in free_pmd_range(), which ended up trying to free an object that was not aligned on a page boundary. Now 3-level page tables should work with 4KB, 8KB and 64KB pages. Signed-off-by: Matt Fleming <matt@console-pimps.org>
* | Merge branch 'sh/stable-updates'Paul Mundt2010-01-041-4/+3
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| * sh: Don't default enable PMB support.Paul Mundt2010-01-041-1/+0
| | | | | | | | | | | | | | | | | | This has the adverse effect of converting many 29bit configs to 32bit mode, while this is a change that needs to be done manually for each platform. Turn it off by default in order to cut down on spurious bug reports. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: Disable PMB for SH4AL-DSP CPUs.Paul Mundt2010-01-041-3/+3
| | | | | | | | | | | | | | | | | | While the PMB is available on SH-4A parts, SH4AL-DSP parts exclude it altogether. As such, explicitly disable PMB support for these parts. If this changes in the future for newer subtypes, this will have to be made more fine-grained. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | Merge branches 'sh/g3-prep' and 'sh/stable-updates'Paul Mundt2009-12-241-6/+2
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| * sh: Ensure all PG_dcache_dirty pages are written back.Markus Pietrek2009-12-241-6/+2
| | | | | | | | | | | | | | | | | | | | | | With some of the cache rework an address aliasing optimization was added, but this managed to fail on certain mappings resulting in pages with PG_dcache_dirty set never writing back their dcache lines. This patch reverts to the earlier behaviour of simply always writing back when the dirty bit is set. Signed-off-by: Markus Pietrek <Markus.Pietrek@emtrion.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: Definitions for 3-level page table layoutMatt Fleming2009-12-173-3/+30
|/ | | | | | | | | | | | | | | | | If using 64-bit PTEs and 4K pages then each page table has 512 entries (as opposed to 1024 entries with 32-bit PTEs). Unlike MIPS, SH follows the convention that all structures in the page table (pgd_t, pmd_t, pgprot_t, etc) must be the same size. Therefore, 64-bit PTEs require 64-bit PGD entries, etc. Using 2-levels of page tables and 64-bit PTEs it is only possible to map 1GB of virtual address space. In order to map all 4GB of virtual address space we need to adopt a 3-level page table layout. This actually works out better for CONFIG_SUPERH32 because we only waste 2 PGD entries on the P1 and P2 areas (which are untranslated) instead of 256. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* Merge branch 'master' of ↵Paul Mundt2009-12-151-1/+2
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
| * fix broken aliasing checks for MAP_FIXED on sparc32, mips, arm and shAl Viro2009-12-111-1/+2
| | | | | | | | | | | | | | | | We want addr - (pgoff << PAGE_SHIFT) consistently coloured... Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Hugh Dickins <hugh.dickins@tiscali.co.uk> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* | sh: wire up vmallocinfo support in ioremap() implementations.Paul Mundt2009-12-142-8/+8
| | | | | | | | | | | | | | | | This wires up the caller information for the ioremap VMA, which allows for more helpful caller tracking via /proc/vmallocinfo. Follows the x86 and powerpc changes of the same nature. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: NUMA lmb fixesMagnus Damm2009-12-091-2/+11
| | | | | | | | | | | | | | | | | | This patch updates the NUMA version of setup_memory() with UMA code changes and also modifies the last argument to lmb_alloc_base() to use an address instead of pfn. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: fix size calculation for NUMA node 0Magnus Damm2009-12-091-1/+1
| | | | | | | | | | | | | | | | | | Fix the NUMA size calculation for node 0. Do the same as the UMA version of setup_memory() and use address instead of pfn when calculating the size. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: Can't compare physical and virtual addresses for aliasesMatt Fleming2009-12-091-2/+1
|/ | | | | | | | It does not make sense to compare virtual and physical addresses for aliasing, only virtual addresses can be compared for aliases. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Drop associative writes for SH-4 cache flushes.Matt Fleming2009-12-041-2/+2
| | | | | | | | | | | | | | | | | | | When flushing/invalidating the icache/dcache via the memory-mapped IC/OC address arrays, the associative bit should only be used in conjunction with virtual addresses. However, we currently flush cache lines based on physical address, so stop using the associative bit. It is a better strategy to use non-associative writes (and physical tags) for flushing the caches anyway, because flushing by virtual address (as with the A-bit set) requires a valid TLB entry for that virtual address. If one does not exist in the TLB no exception is generated and the flush is silently ignored. This is also future-proofing for SH-4A parts which are gradually phasing out associative writes to the cache array due to the aforementioned case of certain flushes silently turning in to nops. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Partial revert of copy/clear_user_highpage() optimizations.Paul Mundt2009-12-041-53/+13
| | | | | | | These still require more testing, so revert them for now. We keep the off-by-1 in the fixmap colouring and drop the rest. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Improve performance of SH4 versions of copy/clear_user_highpageStuart Menefy2009-11-241-13/+53
| | | | | | | | | | | | | | | | | | | | The previous implementation of clear_user_highpage and copy_user_highpage checked to see if there was a D-cache aliasing issue between the user and kernel mappings of a page, but if there was they always did a flush with writeback on the dirtied kernel alias. However as we now have the ability to map a page into kernel space with the same cache colour as the user mapping, there is no need to write back this data. Currently we also invalidate the kernel alias as a precaution, however I'm not sure if this is actually required. Also correct the definition of FIX_CMAP_END so that the mappings created by kmap_coherent() are actually at the correct colour. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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