summaryrefslogtreecommitdiffstats
path: root/arch/x86/kvm/vmx.h
Commit message (Collapse)AuthorAgeFilesLines
* KVM: VMX: move vmx.h to include/asmEduardo Habkost2008-12-311-367/+0
| | | | | | | | vmx.h will be used by core code that is independent of KVM, so I am moving it outside the arch/x86/kvm directory. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com>
* KVM: VMX: Move private memory slot positionSheng Yang2008-12-311-2/+3
| | | | | | | | | | | PCI device assignment would map guest MMIO spaces as separate slot, so it is possible that the device has more than 2 MMIO spaces and overwrite current private memslot. The patch move private memory slot to the top of userspace visible memory slots. Signed-off-by: Sheng Yang <sheng@linux.intel.com> Signed-off-by: Avi Kivity <avi@redhat.com>
* KVM: VMX: Add PAT support for EPTSheng Yang2008-12-311-0/+7
| | | | | | | | | | | GUEST_PAT support is a new feature introduced by Intel Core i7 architecture. With this, cpu would save/load guest and host PAT automatically, for EPT memory type in guest depends on MSR_IA32_CR_PAT. Also add save/restore for MSR_IA32_CR_PAT. Signed-off-by: Sheng Yang <sheng@linux.intel.com> Signed-off-by: Avi Kivity <avi@redhat.com>
* KVM: VMX: Set IGMT bit in EPT entrySheng Yang2008-11-111-0/+1
| | | | | | | | | | | | | There is a potential issue that, when guest using pagetable without vmexit when EPT enabled, guest would use PAT/PCD/PWT bits to index PAT msr for it's memory, which would be inconsistent with host side and would cause host MCE due to inconsistent cache attribute. The patch set IGMT bit in EPT entry to ignore guest PAT and use WB as default memory type to protect host (notice that all memory mapped by KVM should be WB). Signed-off-by: Sheng Yang <sheng@linux.intel.com> Signed-off-by: Avi Kivity <avi@redhat.com>
* x86: Move FEATURE_CONTROL bits to msr-index.hSheng Yang2008-10-151-3/+0
| | | | | | | For MSR_IA32_FEATURE_CONTROL is already there. Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: VMX: Rename IA32_FEATURE_CONTROL bitsSheng Yang2008-10-151-2/+2
| | | | | Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: VMX: Rename misnamed msr bitsSheng Yang2008-10-151-2/+2
| | | | | | | | MSR_IA32_FEATURE_LOCKED is just a bit in fact, which shouldn't be prefixed with MSR_. So is MSR_IA32_FEATURE_VMXON_ENABLED. Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* Merge branch 'x86/unify-cpu-detect' into x86-v28-for-linus-phase4-DIngo Molnar2008-10-111-15/+0
|\ | | | | | | | | | | | | Conflicts: arch/x86/kernel/cpu/common.c arch/x86/kernel/signal_64.c include/asm-x86/cpufeature.h
| * x86: move VMX MSRs to msr-index.hSheng Yang2008-09-101-15/+0
| | | | | | | | | | | | | | | | They are hardware specific MSRs, and we would use them in virtualization feature detection later. Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | KVM: VMX: Always return old for clear_flush_young() when using EPTSheng Yang2008-09-111-2/+0
|/ | | | | | | As well as discard fake accessed bit and dirty bit of EPT. Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: VMX: Enable NMI with in-kernel irqchipSheng Yang2008-07-201-1/+11
| | | | | Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: VMX: Enable EPT feature for KVMSheng Yang2008-05-041-0/+9
| | | | | Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: VMX: Prepare an identity page table for EPT in real modeSheng Yang2008-05-041-0/+3
| | | | | | | | [aliguory: plug leak] Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Add kvm_x86_ops get_tdp_level()Sheng Yang2008-05-041-0/+1
| | | | | | | | The function get_tdp_level() provided the number of tdp level for EPT and NPT rather than the NPT specific macro. Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: VMX: EPT Feature DetectionSheng Yang2008-05-041-0/+25
| | | | | Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: VMX: fix typo in VMX header defineRyan Harper2008-04-271-2/+2
| | | | | | | | | Looking at Intel Volume 3b, page 148, table 20-11 and noticed that the field name is 'Deliver' not 'Deliever'. Attached patch changes the define name and its user in vmx.c Signed-off-by: Ryan Harper <ryanh@us.ibm.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: VMX: Enable Virtual Processor Identification (VPID)Sheng Yang2008-04-271-0/+6
| | | | | | | | | | | | To allow TLB entries to be retained across VM entry and VM exit, the VMM can now identify distinct address spaces through a new virtual-processor ID (VPID) field of the VMCS. [avi: drop vpid_sync_all()] [avi: add "cc" to asm constraints] Signed-off-by: Sheng Yang <sheng.yang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Move arch dependent files to new directory arch/x86/kvm/Avi Kivity2008-01-301-0/+324
This paves the way for multiple architecture support. Note that while ioapic.c could potentially be shared with ia64, it is also moved. Signed-off-by: Avi Kivity <avi@qumranet.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 09:43:47 +0000