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* xtensa: support coprocessors on SMPMax Filippov2022-05-011-32/+90
| | | | | | | | | | | | | | | | | | | | | | | Current coprocessor support on xtensa only works correctly on uniprocessor configurations. Make it work on SMP too and keep it lazy. Make coprocessor_owner array per-CPU and move it to struct exc_table for easy access from the fast_coprocessor exception handler. Allow task to have live coprocessors only on single CPU, record this CPU number in the struct thread_info::cp_owner_cpu. Change struct thread_info::cpenable meaning to be 'coprocessors live on cp_owner_cpu'. Introduce C-level coprocessor exception handler that flushes and releases live coprocessors of the task taking 'coprocessor disabled' exception and call it from the fast_coprocessor handler when the task has live coprocessors on other CPU. Make coprocessor_flush_all and coprocessor_release_all work correctly when called from any CPU by sending IPI to the cp_owner_cpu. Add function coprocessor_flush_release_all to do flush followed by release atomically. Add function local_coprocessors_flush_release_all to flush and release all coprocessors on the local CPU and use it to flush coprocessor contexts from the CPU that goes offline. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: get rid of stack frame in coprocessor_flushMax Filippov2022-05-011-6/+5
| | | | | | | | coprocessor_flush is an ordinary function, it can use all registers. Don't reserve stack frame for it and use a7 to preserve a0 around the context saving call. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: merge SAVE_CP_REGS_TAB and LOAD_CP_REGS_TABMax Filippov2022-05-011-48/+37
| | | | | | | | Both tables share the same offset field but the different function pointers. Merge them into single table with 3-element entries to reduce code and data duplication. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: use callx0 opcode in fast_coprocessorMax Filippov2022-05-011-10/+8
| | | | | | | Instead of emulating call0 in fast_coprocessor use that opcode directly. Use 'ret' instead of 'jx a0'. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: fix a7 clobbering in coprocessor context load/storeMax Filippov2022-04-151-2/+2
| | | | | | | | | | | | Fast coprocessor exception handler saves a3..a6, but coprocessor context load/store code uses a4..a7 as temporaries, potentially clobbering a7. 'Potentially' because coprocessor state load/store macros may not use all four temporary registers (and neither FPU nor HiFi macros do). Use a3..a6 as intended. Cc: stable@vger.kernel.org Fixes: c658eac628aa ("[XTENSA] Add support for configurable registers and coprocessors") Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: move coprocessor_flush to the .text sectionMax Filippov2021-03-081-31/+33
| | | | | | | | | | | | | | | coprocessor_flush is not a part of fast exception handlers, but it uses parts of fast coprocessor handling code that's why it's in the same source file. It uses call0 opcode to invoke those parts so there are no limitations on their relative location, but the rest of the code calls coprocessor_flush with call8 and that doesn't work when vectors are placed in a different gigabyte-aligned area than the rest of the kernel. Move coprocessor_flush from the .exception.text section to the .text so that it's reachable from the rest of the kernel with call8. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: move fast exception handlers close to vectorsMax Filippov2020-02-041-3/+2
| | | | | | | | | | | | On XIP kernels it makes sense to have exception vectors and fast exception handlers together (in a fast memory). In addition, with MTD XIP support both vectors and fast exception handlers must be outside of the FLASH. Add section .exception.text and move fast exception handlers to it. Put it together with vectors when vectors are outside of the .text. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: drop unused function fast_coprocessor_doubleMax Filippov2020-02-011-7/+0
| | | | | | | | | fast_coprocessor_double is not used since commit c658eac628aa ("[XTENSA] Add support for configurable registers and coprocessors"). Remove it. There should be no coprocessor exceptions generated in the exception handling paths while PS.EXCM is set. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: drop unneeded headers from coprocessor.SMax Filippov2019-11-261-9/+1
| | | | | | | A bunch of irrelevant headers is included into coprocessor.S. Remove them and add necessary asm/regs.h. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: fix build for cores with coprocessorsMax Filippov2019-07-241-0/+1
| | | | | | | | | Assembly entry/return abstraction change didn't add asmmacro.h include statement to coprocessor.S, resulting in references to undefined macros abi_entry and abi_ret on cores that define XTENSA_HAVE_COPROCESSORS. Fix that by including asm/asmmacro.h from the coprocessor.S. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: abstract 'entry' and 'retw' in assembly codeMax Filippov2019-07-081-2/+5
| | | | | | | | | | | Provide abi_entry, abi_entry_default, abi_ret and abi_ret_default macros that allocate aligned stack frame in windowed and call0 ABIs. Provide XTENSA_SPILL_STACK_RESERVE macro that specifies required stack frame size when register spilling is involved. Replace all uses of 'entry' and 'retw' with the above macros. This makes most of the xtensa assembly code ready for XEA3 and call0 ABI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: simplify coprocessor.SMax Filippov2018-12-041-18/+18
| | | | | | | Use addresses instead of offsets and drop unneeded offset -> address calculations. Don't generate any code for undefined coprocessors. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: drop unused coprocessor helper functionsMax Filippov2018-12-031-65/+3
| | | | | | | coprocessor_save, coprocessor_load and coprocessor_restore are neither used nor exported for use by modules. Drop them. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: use call instead of callx in assembly codeMax Filippov2017-12-101-2/+1
| | | | | | | | Now that xtensa assembly sources are compiled with -mlongcalls let the assembler and linker relax call instructions into l32r + callx where needed. This change makes the code cleaner and potentially a bit faster. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: drop unused fast_io_protect functionMax Filippov2017-05-011-24/+0
| | | | | | fast_io_protect is not used anywhere, drop its definition. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: split uaccess.h into C and asm sidesAl Viro2016-09-271-1/+1
| | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* xtensa: keep a3 and excsave1 on entry to exception handlersMax Filippov2013-09-061-5/+4
| | | | | | | | | Based on the SMP patch by Joe Taylor and subsequent fixes. Preserve exception table pointer (normally stored in excsave1 SR) as it cannot be easily restored in SMP environment. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: clean up files to make them code-style compliantChris Zankel2012-12-181-2/+1
| | | | | | | Remove heading and trailing spaces, trim trailing lines, and wrap lines that are longer than 80 characters. Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: provide proper assembler function boundaries with ENDPROC()Chris Zankel2012-12-181-0/+22
| | | | | | Use ENDPROC() to mark the end of assembler functions. Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: reorganize SR referencingMax Filippov2012-10-151-10/+10
| | | | | | | | | | - reference SRs by names where possible, not by numbers; - get rid of __stringify around SR names where possible; - remove unneeded SR names from asm/regs.h; - add SREG_ prefix to remaining SR names; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* [XTENSA] Add support for configurable registers and coprocessorsChris Zankel2008-02-131-154/+289
| | | | | | | | | | | | | | | | | | | | The Xtensa architecture allows to define custom instructions and registers. Registers that are bound to a coprocessor are only accessible if the corresponding enable bit is set, which allows to implement a 'lazy' context switch mechanism. Other registers needs to be saved and restore at the time of the context switch or during interrupt handling. This patch adds support for these additional states: - save and restore registers that are used by the compiler upon interrupt entry and exit. - context switch additional registers unbound to any coprocessor - 'lazy' context switch of registers bound to a coprocessor - ptrace interface to provide access to additional registers - update configuration files in include/asm-xtensa/variant-fsf Signed-off-by: Chris Zankel <chris@zankel.net>
* [PATCH] xtensa: remove extra header filesChris Zankel2006-12-101-1/+1
| | | | | | | | | | | The Xtensa port contained many header files that were never needed. This rather lengthy patch removes all those files. Unfortunately, there were many dependencies that needed to be updated, so this patch touches quite a few source files. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-301-1/+0
| | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* [PATCH] xtensa: Architecture support for Tensilica Xtensa Part 3Chris Zankel2005-06-241-0/+201
The attached patches provides part 3 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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