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* xtensa: use register window specific opcodes only when presentMax Filippov2021-10-181-0/+2
| | | | | | | | | xtensa core may be configured without register windows support, don't use register window specific opcodes in that case. Use window register specific opcodes to initialize hardware or reset core to a known state regardless of the chosen ABI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: implement call0 ABI support in assemblyMax Filippov2021-10-181-10/+12
| | | | | | | | | Replace hardcoded register and opcode names with ABI-agnostic macros. Add register save/restore code where necessary. Conditionalize windowed only or call0 only code. Add stack initialization matching _switch_to epilogue to copy_thread. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: Couple of typo fixesBhaskar Chowdhury2021-04-041-2/+2
| | | | | | | | | s/contans/contains/ s/desination/destination/ Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> Message-Id: <20210325040832.26018-1-unixbhaskar@gmail.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: add XIP kernel supportMax Filippov2019-11-261-0/+7
| | | | | | | | | | | | | | | | | | XIP (eXecute In Place) kernel image is the image that can be run directly from ROM, using RAM only for writable data. XIP xtensa kernel differs from regular xtensa kernel in the following ways: - it has exception/IRQ vectors merged into text section. No vectors relocation takes place at kernel startup. - .data/.bss location must be specified in the kernel configuration, its content is copied there in the _startup function. - .init.text is merged with the rest of text and is executed from ROM. - when MMU is used the virtual address where the kernel will be mapped must be specified in the kernel configuration. It may be in the KSEG or in the KIO, __pa macro is adjusted to be able to handle both. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: fix section name for start_infoMax Filippov2019-10-201-3/+3
| | | | | | | .data.init.refok has been removed from the kernel long ago, replaced with __REFDATA. Fix start_info definition. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: clean up PS_WOE_BIT usageMax Filippov2019-09-011-1/+1
| | | | | | | PS_WOE_BIT is mainly used to generate PS.WOE mask in the code. Introduce PS_WOE_MASK macro and use it instead. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: SMP: fix secondary CPU initializationMax Filippov2019-01-261-1/+4
| | | | | | | | | | | | - add missing memory barriers to the secondary CPU synchronization spin loops; add comment to the matching memory barrier in the boot_secondary and __cpu_die functions; - use READ_ONCE/WRITE_ONCE to access cpu_start_id/cpu_start_ccount instead of reading/writing them directly; - re-initialize cpu_running every time before starting secondary CPU to flush possible previous CPU startup results. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: don't use l32r opcode directlyMax Filippov2018-12-051-6/+2
| | | | | | | | | xtensa assembler is capable of representing register loads with either movi + addmi, l32r or const16, depending on the core configuration. Don't use '.literal' and 'l32r' directly in the code, use 'movi' and let the assembler relax them. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: fix boot parameters address translationMax Filippov2018-11-141-2/+5
| | | | | | | | | | | | | | The bootloader may pass physical address of the boot parameters structure to the MMUv3 kernel in the register a2. Code in the _SetupMMU block in the arch/xtensa/kernel/head.S is supposed to map that physical address to the virtual address in the configured virtual memory layout. This code haven't been updated when additional 256+256 and 512+512 memory layouts were introduced and it may produce wrong addresses when used with these layouts. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: rework noMMU cache attributes initializationMax Filippov2018-08-131-0/+2
| | | | | | | | | Marking default memory region as cached is not always sufficient and is not flexible. Allow specifying cache attributes for the whole memory address space with new config entry MEMMAP_CACHEATTR. Apply it after cache initialization. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: use call instead of callx in assembly codeMax Filippov2017-12-101-7/+3
| | | | | | | | Now that xtensa assembly sources are compiled with -mlongcalls let the assembler and linker relax call instructions into l32r + callx where needed. This change makes the code cleaner and potentially a bit faster. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: cleanup MMU setup and kernel layout macrosMax Filippov2016-07-241-1/+1
| | | | | | | | | | | | | | | | Make kernel load address explicit, independent of the selected MMU configuration and configurable from Kconfig. Do not restrict it to the first 512MB of the physical address space. Cleanup kernel memory layout macros: - rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR; - drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS; - introduce PHYS_OFFSET and use it in __va and __pa definitions; - synchronize MMU/noMMU vectors, drop unused NMI vector; - replace hardcoded vectors offset of 0x3000 with Kconfig symbol. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: use context structure for debug exceptionsMax Filippov2016-03-111-5/+0
| | | | | | | | | | | | | | | With implementation of data breakpoints debug exceptions raised when PS.EXCM is set need to be handled, e.g. window overflow code can write to watched userspace address. Currently debug exception handler uses EXCSAVE and DEPC SRs to save temporary registers, but DEPC may not be available when PS.EXCM is set and more space will be needed to save additional state. Reorganize debug context: create per-CPU structure debug_table instance and store its address in the EXCSAVE<debug level> instead of debug_exception function address. Expand this structure when more save space is needed. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: clear all DBREAKC registers on startMax Filippov2016-03-111-1/+1
| | | | | | | | | | | | There are XCHAL_NUM_DBREAK registers, clear them all. This also fixes cryptic assembler error message with binutils 2.25 when XCHAL_NUM_DBREAK is 0: as: out of memory allocating 18446744073709551575 bytes after a total of 495616 bytes Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: fixes for configs without loop optionMax Filippov2015-11-021-1/+1
| | | | | | | | | | | | | | | | Build-time fixes: - make lbeg/lend/lcount save/restore conditional on kernel entry; - don't clear lcount in platform_restart functions unconditionally. Run-time fixes: - use correct end of range register in __endla paired with __loopt, not the unused temporary register. This fixes .bss zero-initialization. Update comments in asmmacro.h; - don't clobber a10 in the usercopy that leads to access to unmapped memory. Cc: <stable@vger.kernel.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: move vecbase SR initialization to _startupMax Filippov2014-10-211-0/+5
| | | | | | | | | Instead of initializing vecbase in initialize_mmu macro, which may be expanded either in Image.elf reset vector hadler or in the kernel head.S, both times only when CONFIG_MMU is enabled, do this initialization once in _startup function. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* xtensa: implement CPU hotplugMax Filippov2014-01-141-1/+50
| | | | | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: add SMP supportMax Filippov2014-01-141-43/+87
| | | | | | | | | This is largely based on SMP code from the xtensa-2.6.29-smp tree by Piet Delaney, Marc Gauthier, Joe Taylor, Christian Zankel (and possibly other Tensilica folks). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: adjust boot parameters address when ↵Max Filippov2013-07-081-0/+9
| | | | | | | | | | | | | | | | INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX is selected The virtual address of boot parameters chain is passed to the kernel via a2 register. Adjust it in case it is remapped during MMUv3 -> MMUv2 mapping change, i.e. when it is in the first 128M. Also fix interpretation of initrd and FDT addresses passed in the boot parameters: these are physical addresses. Cc: stable@vger.kernel.org Reported-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: add MMU v3 supportMax Filippov2013-05-091-10/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB way 6: Way 6 (512 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0x00000000 0x00000000 0x01 0x03 RWX Bypass 0x20000000 0x20000000 0x01 0x03 RWX Bypass 0x40000000 0x40000000 0x01 0x03 RWX Bypass 0x60000000 0x60000000 0x01 0x03 RWX Bypass 0x80000000 0x80000000 0x01 0x03 RWX Bypass 0xa0000000 0xa0000000 0x01 0x03 RWX Bypass 0xc0000000 0xc0000000 0x01 0x03 RWX Bypass 0xe0000000 0xe0000000 0x01 0x03 RWX Bypass This patch adds remapping code at the reset vector or at the kernel _start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that reconfigures MMUv3 as MMUv2: Way 5 (128 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0xd0000000 0x00000000 0x01 0x07 RWX WB 0xd8000000 0x00000000 0x01 0x03 RWX Bypass Way 6 (256 MB) Vaddr Paddr ASID Attr RWX Cache ---------- ---------- ---- ---- --- ------- 0xe0000000 0xf0000000 0x01 0x07 RWX WB 0xf0000000 0xf0000000 0x01 0x03 RWX Bypass Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: fix ibreakenable register updateMax Filippov2013-05-091-0/+2
| | | | | | | | | | | | Only set the register when there is at least one ibreak register, otherwise the build fails: arch/xtensa/kernel/head.S:105: Error: invalid register 'ibreakenable' for 'wsr' instruction arch/xtensa/platforms/iss/setup.c:67: Error: invalid register 'ibreakenable' for 'wsr' instruction Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: dispatch medium-priority interruptsMarc Gauthier2013-02-231-4/+5
| | | | | | | | | | Add support for dispatching medium-priority interrupts, that is, interrupts of priority levels 2 to EXCM_LEVEL. IRQ handling may be preempted by higher priority IRQ. Signed-off-by: Marc Gauthier <marc@tensilica.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: initialize CPENABLE SR when core has oneMax Filippov2012-12-181-1/+1
| | | | | | | | | XCHAL_CP_NUM is defined in variant/tie.h and it is not included by head.S, leaving CPENABLE register uninitialised. XCHAL_HAVE_CP is defined in variant/core.h to 1 when core has CPENABLE SR. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: reset all timers on initializationMax Filippov2012-12-181-1/+1
| | | | | | | There are XCHAL_NUM_TIMERS, reset them all. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: initialize atomctl SRMax Filippov2012-12-181-0/+3
| | | | | | | | In order to use S32C1I instruction on cores with ATOMCTL SR the register must be properly initialized. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: provide proper assembler function boundaries with ENDPROC()Chris Zankel2012-12-181-4/+10
| | | | | | Use ENDPROC() to mark the end of assembler functions. Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: reorganize SR referencingMax Filippov2012-10-151-18/+18
| | | | | | | | | | - reference SRs by names where possible, not by numbers; - get rid of __stringify around SR names where possible; - remove unneeded SR names from asm/regs.h; - add SREG_ prefix to remaining SR names; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: Fixes due to bss boundary symbol name changes.Chris Zankel2010-05-011-2/+2
| | | | | | The bss start and end symbols have changed to __bss_start and __bss_stop. Signed-off-by: Chris Zankel <chris@zankel.net>
* Use macros for .bss.page_aligned section.Tim Abbott2009-09-211-1/+1
| | | | | | | | | | | | | | This patch changes the remaining direct references to .bss.page_aligned in C and assembly code to use the macros in include/linux/linkage.h. Signed-off-by: Tim Abbott <tabbott@ksplice.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Cc: Chris Zankel <chris@zankel.net> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
* xtensa: convert to use __HEAD and HEAD_TEXT macros.Tim Abbott2009-04-261-1/+2
| | | | | | | Signed-off-by: Tim Abbott <tabbott@mit.edu> Cc: Chris Zankel <chris@zankel.net> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* xtensa: make startup code discardableDaniel Glöckner2009-04-021-1/+1
| | | | | | | | Move it from .text to .init.text to get rid of it after boot and prevent illegal section references. Signed-off-by: Daniel Glöckner <dg@emlix.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* xtensa: nommu supportJohannes Weiner2009-04-021-1/+2
| | | | | | | Add support for !CONFIG_MMU setups. Signed-off-by: Johannes Weiner <jw@emlix.com> Signed-off-by: Chris Zankel <chris@zankel.net>
* [XTENSA] Move common sections into bss sectionsChris Zankel2007-05-311-8/+11
| | | | | | | | Move the fields of the COMMON sections 'swapper_pg_dir' and 'empty_zero_page' to the BSS section. Remove the unused COMMON sections 'emtpy_bad_page_table' and 'empty_bad_page'. Signed-off-by: Chris Zankel <chris@zankel.net>
* [PATCH] xtensa: remove extra header filesChris Zankel2006-12-101-25/+28
| | | | | | | | | | | The Xtensa port contained many header files that were never needed. This rather lengthy patch removes all those files. Unfortunately, there were many dependencies that needed to be updated, so this patch touches quite a few source files. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-301-1/+0
| | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* [PATCH] xtensa: Architecture support for Tensilica Xtensa Part 3Chris Zankel2005-06-241-0/+237
The attached patches provides part 3 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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