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* Merge branch 'next' of ↵Linus Torvalds2010-10-276-229/+147
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (48 commits) DMAENGINE: move COH901318 to arch_initcall dma: imx-dma: fix signedness bug dma/timberdale: simplify conditional ste_dma40: remove channel_type ste_dma40: remove enum for endianess ste_dma40: remove TIM_FOR_LINK option ste_dma40: move mode_opt to separate config ste_dma40: move channel mode to a separate field ste_dma40: move priority to separate field ste_dma40: add variable to indicate valid dma_cfg async_tx: make async_tx channel switching opt-in move async raid6 test to lib/Kconfig.debug dmaengine: Add Freescale i.MX1/21/27 DMA driver intel_mid_dma: change the slave interface intel_mid_dma: fix the WARN_ONs intel_mid_dma: Add sg list support to DMA driver intel_mid_dma: Allow DMAC2 to share interrupt intel_mid_dma: Allow IRQ sharing intel_mid_dma: Add runtime PM support DMAENGINE: define a dummy filter function for ste_dma40 ...
| * Merge branch 'dma40' into dmaengineDan Williams2010-10-192-50/+22
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| | * ste_dma40: remove channel_typeRabin Vincent2010-10-191-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | It has been replaced with separate fields. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | * ste_dma40: remove enum for endianessRabin Vincent2010-10-192-11/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | A bool will suffice. The default is little endian. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | * ste_dma40: remove TIM_FOR_LINK optionRabin Vincent2010-10-192-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This does not seem to be implemented. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | * ste_dma40: move mode_opt to separate configRabin Vincent2010-10-192-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defaults are "basic mode" for physical channels, and "logical source logical destination" for logical channels. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | * ste_dma40: move channel mode to a separate fieldRabin Vincent2010-10-192-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | And keep it logical by default. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | * ste_dma40: move priority to separate fieldRabin Vincent2010-10-192-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | And keep it low priority by default. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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| *---. \ Merge branches 'dma40', 'pl08x', 'fsldma', 'imx' and 'intel-mid' into dmaengineDan Williams2010-10-074-143/+86
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| | | | * dmaengine: Add Freescale i.MX SDMA supportSascha Hauer2010-10-053-6/+86
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Freescale i.MX SDMA engine. The SDMA engine is a scatter/gather DMA engine which is implemented as a seperate coprocessor. SDMA needs its own firmware which is requested using the standard request_firmware mechanism. The firmware has different entry points for each peripheral type, so drivers have to pass the peripheral type to the DMA engine which in turn picks the correct firmware entry point from a table contained in the firmware image itself. The original Freescale code also supports support for transfering data to the internal SRAM which needs different entry points to the firmware. Support for this is currently not implemented. Also, support for the ASRC (asymmetric sample rate converter) is skipped. I took a very simple approach to implement dmaengine support. Only a single descriptor is statically assigned to a each channel. This means that transfers can't be queued up but only a single transfer is in progress. This simplifies implementation a lot and is sufficient for the usual device/memory transfers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Linus Walleij <linus.ml.walleij@gmail.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | * fsldma: improved DMA_SLAVE supportIra Snyder2010-10-071-137/+0
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the generic DMAEngine API has support for scatterlist to scatterlist copying, the device_prep_slave_sg() portion of the DMA_SLAVE API is no longer necessary and has been removed. However, the device_control() portion of the DMA_SLAVE API is still useful to control device specific parameters, such as externally controlled DMA transfers and maximum burst length. A special dma_ctrl_cmd has been added to enable externally controlled DMA transfers. This is currently specific to the Freescale DMA controller, but can easily be made generic when another user is found. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | DMAENGINE: define a dummy filter function for ste_dma40Linus Walleij2010-10-071-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | All platform data has to be made conditional on CONFIG_STEDMA40 or we can provide a simple dummy filter functions as to avoid cluttering the code with other #ifdef:s. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | DMAENGINE: Remove stedma40_set_psize and pre_transfer hook in ste_dma40Per Forlin2010-10-071-23/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove obsolete pre_transfer hook in stedma40_chan_cfg. The intent of this hook is merely to handle burst size compensation for ux500 variant MMCI. Remove obsolete stedma40_set_psize since it is only called from pre_transfer. DMAEngine device_control replaces the functionality of stedma40_set_psize. Signed-off-by: Per Forlin <per.forlin@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | DMAENGINE: ste_dma40: added kernel doc for structJonas Aaberg2010-09-221-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | The half-channel struct was undocumented. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | DMAENGINE: ste_dma40: removed non-used variable from structJonas Aaberg2010-09-222-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | The reqrite of the LCLA code rendered this variable unused. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | DMAENGINE: ste_dma40: code clean-upJonas Aaberg2010-09-221-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes non functional code clean up changes, file header updates and a few magic numbers got defined. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | DMAENGINE: ste_dma40: config checksLinus Walleij2010-09-221-1/+1
| |/ | | | | | | | | | | | | | | Added various configuration checks. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300Linus Torvalds2010-10-27137-1944/+9384
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300: (44 commits) MN10300: Save frame pointer in thread_info struct rather than global var MN10300: Change "Matsushita" to "Panasonic". MN10300: Create a defconfig for the ASB2364 board MN10300: Update the ASB2303 defconfig MN10300: ASB2364: Add support for SMSC911X and SMC911X MN10300: ASB2364: Handle the IRQ multiplexer in the FPGA MN10300: Generic time support MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit support MN10300: Map userspace atomic op regs as a vmalloc page MN10300: And Panasonic AM34 subarch and implement SMP MN10300: Delete idle_timestamp from irq_cpustat_t MN10300: Make various interrupt priority settings configurable MN10300: Optimise do_csum() MN10300: Implement atomic ops using atomic ops unit MN10300: Make the FPU operate in non-lazy mode under SMP MN10300: SMP TLB flushing MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control MN10300: Make the use of PIDR to mark TLB entries controllable MN10300: Rename __flush_tlb*() to local_flush_tlb*() MN10300: AM34 erratum requires MMUCTR read and write on exception entry ...
| * | MN10300: Save frame pointer in thread_info struct rather than global varDavid Howells2010-10-2714-145/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Save the current exception frame pointer in the thread_info struct rather than in a global variable as the latter makes SMP tricky, especially when preemption is also enabled. This also replaces __frame with current_frame() and rearranges header file inclusions to make it all compile. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
| * | MN10300: Change "Matsushita" to "Panasonic".Akira Takeuchi2010-10-273-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Change externally visible "Matsushita" instances to "Panasonic" throughout the MN10300 arch code. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Create a defconfig for the ASB2364 boardAkira Takeuchi2010-10-271-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | Create a defconfig for the ASB2364 board. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Update the ASB2303 defconfigAkira Takeuchi2010-10-271-0/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: ASB2364: Add support for SMSC911X and SMC911XAkira Takeuchi2010-10-275-0/+233
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for SMSC911X and SMC911X for the ASB2364 unit. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com> cc: steve.glendinning@smsc.com cc: netdev@vger.kernel.org
| * | MN10300: ASB2364: Handle the IRQ multiplexer in the FPGADavid Howells2010-10-277-19/+166
| | | | | | | | | | | | | | | | | | | | | Handle the IRQ multiplexer in the FPGA by implementing a cascade interrupt driver for it. Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Generic time supportMark Salter2010-10-2712-115/+401
| | | | | | | | | | | | | | | | | | | | | Implement generic time support for MN10300. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit supportMark Salter2010-10-271-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Use an ELF HWCAP flag to indicate to the process that the CPU provides LL/SC equivalent atomic operations unit support in addition to BSET/BCLR. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Map userspace atomic op regs as a vmalloc pageMark Salter2010-10-272-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM34 processor has an atomic operation that's the equivalent of LL/SC on other architectures. However, rather than being done through a pair of instructions, it's driven by writing to a pair of memory-mapped CPU control registers. One set of these registers (AARU/ADRU/ASRU) is available for use by userspace, but for userspace to access them a PTE must be set up to cover the region. This is done by dedicating the first vmalloc region page to this purpose, setting the permissions on its PTE such that userspace can access the page. glibc is hardcoded to expect the registers to be there. The way atomic ops are done through these registers is straightforward: (1) Write the address of the word you wish to access into AARU. This causes the CPU to go and fetch that word and load it into ADRU. The status bits are also cleared in ASRU. (2) The current data value is read from the ADRU register and modified. (3) To alter the data in RAM, the revised data is written back to the ADRU register, which causes the CPU to attempt to write it back. (4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch), ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then must be checked to confirm that the operation wasn't aborted. If any of the watches have been set to true, the operation was aborted. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: And Panasonic AM34 subarch and implement SMPAkira Takeuchi2010-10-2779-481/+4494
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Delete idle_timestamp from irq_cpustat_tAkira Takeuchi2010-10-272-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Delete idle_timestamp from irq_cpustat_t as it's an unread relic. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Make various interrupt priority settings configurableAkira Takeuchi2010-10-272-6/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the settings of interrupt priorities used by various services configurable at run time. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Optimise do_csum()Akira Takeuchi2010-10-271-27/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Optimise do_csum() to gang up the loads so they're less likely to get interruptions between. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Implement atomic ops using atomic ops unitMark Salter2010-10-272-47/+351
| | | | | | | | | | | | | | | | | | | | | | | | Implement atomic ops using the atomic ops unit available in the AM34 CPU. This allows the equivalent of the LL/SC instructions to be found on other CPUs. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Make the FPU operate in non-lazy mode under SMPAkira Takeuchi2010-10-2714-248/+440
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the FPU operate in non-lazy mode under SMP so that when the process that is currently using the FPU migrates to a different CPU, we don't have to ping its previous CPU to flush the FPU context. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: SMP TLB flushingAkira Takeuchi2010-10-274-29/+290
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement global TLB flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB controlAkira Takeuchi2010-10-273-47/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits are a more suitable layout. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Make the use of PIDR to mark TLB entries controllableAkira Takeuchi2010-10-274-62/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make controllable the use of the PIDR register to mark TLB entries as belonging to particular processes. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Rename __flush_tlb*() to local_flush_tlb*()David Howells2010-10-276-28/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename __flush_tlb*() to local_flush_tlb*() as it's more appropriate, and ready to differentiate local from global TLB flushes when SMP is introduced. Whilst we're at it, get rid of __flush_tlb_global() and make local_flush_tlb_page() take an mm_struct pointer rather than VMA pointer. Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: AM34 erratum requires MMUCTR read and write on exception entryAkira Takeuchi2010-10-273-6/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | An AM34 erratum requires MMUCTR read and write on entry to certain exceptions, prior to EPSW.NMID being cleared to allow NMIs to happen. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Make the boot wrapper able to use writeback cachingAkira Takeuchi2010-10-271-1/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the boot wrapper able to use writeback caching, including flushing the cache before jumping to the main kernel. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Cache: Implement SMP global cache flushingAkira Takeuchi2010-10-279-15/+535
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement SMP global cache flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Allow some cacheflushes to be avoided if cache snooping is availableDavid Howells2010-10-279-96/+309
| | | | | | | | | | | | | | | | | | | | | The AM34 core is able to do cache snooping, and so can skip some of the cache flushing. Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: AM34: Add cacheflushing by using the AM34 purge registersAkira Takeuchi2010-10-274-1/+678
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM34 CPU core provides an automated way of purging the cache rather than manually iterating over all the tags in the cache. Make it possible to use these. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: SMP: Differentiate local cache flushingAkira Takeuchi2010-10-274-112/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Differentiate local cache flushing from global cache flushing so that they can be done differently on SMP systems. Rename the cache functions from: mn10300_[id]cache_*() to: mn10300_[id]_localcache_*() and on a UP system, assign the global labels to the local labels. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Cacheflush functions should take unsigned long addressesAkira Takeuchi2010-10-272-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | The functions that perform cache flushing should take addresses of unsigned long type, not unsigned int. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: AM34: The current cacheflush routines operate by controlling tag regsDavid Howells2010-10-274-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current cache flush and invalidate routines operate by controlling the cache tag registers. Rename the files and add config items to select them. This makes it easier to support the use of other cache flush methods instead, such as the use of AM34's area purge registers, if available. Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Reorder asm/cacheflush.h to put primitives firstDavid Howells2010-10-271-44/+44
| | | | | | | | | | | | | | | | | | | | | | | | Reorder asm/cacheflush.h to put arch primitives first, before the main functions so that the main functions can be inline asm rather than #defines when non-trivial. Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Provide a MN10300_CACHE_ENABLED config optionDavid Howells2010-10-276-10/+13
| | | | | | | | | | | | | | | | | | | | | Provide a MN10300_CACHE_ENABLED config option as inverted logic of MN10300_CACHE_DISABLED to make things simpler. Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Cache: Split cache bits out of arch KconfigDavid Howells2010-10-272-28/+33
| | | | | | | | | | | | | | | | | | Split the cache bits out of arch/mn10300/Kconfig as they're quite complex. Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Remove monitor/JTAG functionsAkira Takeuchi2010-10-274-55/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the monitor trap function and the set_jtag_stub function as they're not really necessary. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
| * | MN10300: Add CPU register bits for AM34Akira Takeuchi2010-10-272-5/+74
| | | | | | | | | | | | | | | | | | | | | | | | Add CPU register declarations for the AM34 subarch. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
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