| Commit message (Collapse) | Author | Age | Files | Lines |
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Fix the following sparse warnings in the OMAP3/4 CPUIdle code:
arch/arm/mach-omap2/cpuidle34xx.c:272:1: warning: symbol 'omap3_idle_dev' was not declared. Should it be static?
arch/arm/mach-omap2/cpuidle34xx.c:274:23: warning: symbol 'omap3_idle_driver' was not declared. Should it be static?
arch/arm/mach-omap2/cpuidle44xx.c:164:1: warning: symbol 'omap4_idle_dev' was not declared. Should it be static?
arch/arm/mach-omap2/cpuidle44xx.c:166:23: warning: symbol 'omap4_idle_driver' was not declared. Should it be static?
Also fix the following checkpatch warnings:
WARNING: please, no space before tabs
#44: FILE: arch/arm/mach-omap2/cpuidle34xx.c:105:
+^I.name = ^I"omap3_idle",$
WARNING: please, no space before tabs
#45: FILE: arch/arm/mach-omap2/cpuidle34xx.c:106:
+^I.owner = ^ITHIS_MODULE,$
ERROR: code indent should use tabs where possible
#211: FILE: arch/arm/mach-omap2/cpuidle44xx.c:74:
+ /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */$
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Booting OMAP4460 Pandaboard ES with a recent u-boot results in this
warning:
WARNING: at arch/arm/mach-omap2/dpll3xxx.c:427 omap3_noncore_dpll_enable+0xf4/0x110()
The OMAP4 DPLL parent clock names only listed the reference clocks,
not the bypass clocks. Fix by adding the bypass clocks to the DPLL
parent lists.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Mike Turquette <mturquette@linaro.org>
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The OMAP4 clock divider "div_iva_hs_clk" is listed in the clock data
as an OMAP HSDIVIDER, but it's actually a power-of-two divider. This
causes a warning during boot on an OMAP4460 Pandaboard-ES with a
recent u-boot:
WARNING: at arch/arm/mach-omap2/clkt_clksel.c:143 omap2_clksel_recalc+0xf4/0x12c()
clock: div_iva_hs_clk: could not find fieldval 0 for parent dpll_core_m5x2_ck
Fix by converting the data for this clock to a power-of-two divider.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Mike Turquette <mturquette@linaro.org>
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Commit d043d87 (ARM: OMAP2+: clockdomain: bypass clockdomain handling
when disabling unused clks) skips the decrementing of a clock-domains
use count if the clocks use count is zero. However, for OMAP4 devices
this is causing the EMU clock-domain to be stuck ON as the use count is
not getting decremented correctly.
The scenario that leads to this problem is described below ...
omap_hwmod_setup_all
--> _setup
--> clkdm_hwmod_enable
--> EMU clock domain usecount = 1
--> _enable_clocks
--> clk_enable
--> trace_clk_div_div usecount = 1
--> clkdm_hwmod_enable
--> EMU clock domain usecount = 2
--> _idle
--> _disable_clocks
--> clk_disable
--> trace_clk_div_div usecount = 0
--> clkdm_hwmod_disable
--> skips decrement of EMU clock domain usecount
because trace_clk_div_div is 0!
--> EMU clock domain usecount = 2
--> clkdm_hwmod_disable
--> EMU clock domain usecount = 1
Hence, due to the order that a clocks use count is decremented and the
clock domain is disabled, it is possible that the clock domain can have
a non-zero use count when the actual clock has a use count of 0.
Therefore, we should only bypass the clock-domain handling when both the
clock-domain and clock in the clock-domain have a use count of 0 and
warn when the clock-domain has a zero use count and the clock has a
non-zero use count.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: fixed checkpatch warning]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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With the latest mainline u-boot bootloader (v2012.10), timers (5-8) in
the ABE power domain are failing to turn-on. The timers never come out
of the disabled state when setting the module-mode field to enable.
The problem was exposed when u-boot was updated to NOT configure and
lock the ABE DPLL on start-up. If the ABE DPLL is configured and locked
by u-boot the problem does not occur. However, if the ABE DPLL is in the
idle low-power bypass state and we attempt to enable a timer in the ABE
power domain, it remains stuck in the disabled state. It appears to be a
problem the timer interface clock as this comes from the ABE DPLL.
If we place the ABE DPLL in the MN-bypass state and not the idle
low-power state, then this problem is not seen.
This problem only appears to occur on OMAP4460 and not OMAP4430.
Workaround this problem by locking the ABE DPLL for OMAP4460 in the
kernel on boot. By locking the ABE DPLL, when clocks from the ABE DPLL
are not being requested the DPLL will transition into a low-power stop
mode.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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On OMAP4 devices, the ABE DPLL has an internal 4X multiplier that can
be enabled or disabled in addition to the standard configurable
multiplier (M) for OMAP DPLLs. When configuring the ABE DPLL the 4X
multiplier is accounted for by checking to see whether it is enabled or
not. However, when calculating a new rate we only check to see if the
rate can be achieved with the current setting for the 4X multiplier.
Enhance the round_rate() function for such DPLLs to see if the rate
can be achieved with the 4X multiplier if it cannot be achieved without
the 4X multiplier.
This change is necessary, because when using the 32kHz clock as the
source clock for the ABE DPLL, the default DPLL frequency for the ABE
DPLL cannot be achieved without enabling the 4X multiplier.
When using the 32kHz clock as the source clock for the ABE DPLL and
attempting to lock the DPLL to 98.304MHz (default frequency), it was
found that the DPLL would fail to lock if the low-power mode for the DPLL
was not enabled. From reviewing boot-loader settings that configure the
ABE DPLL it was found that the low-power mode is enabled when using the
32kHz clock source, however, the documentation for OMAP does not state
that this is a requirement. Therefore, introduce a new function for
OMAP4 devices to see if low-power mode can be enabled when calculating a
new rate to ensure the DPLL will lock.
New variables for the last calculated 4X multiplier and low-power
setting have been added to the dpll data structure as well as variables
defining the bit mask for enabling these features via the DPLL's
control_reg. It is possible that we could eliminate these bit masks from
the dpll data structure as these bit masks are not unique to OMAP4, if
it is preferred.
The function omap3_noncore_program_dpll() has been updated to avoid
passing the calculated values for the multiplier (M) and divider (N) as
these are stored in the clk structure.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Currently all OMAP4 non-core DPLLs use the same function table for
configuring DPLLs. For these DPLLs, the function
omap4_dpll_regm4xen_recalc() is used to recalculate the DPLL rate and
the function omap4_dpll_regm4xen_round_rate() is used to calculate the
closest rate to that requested. However, these omap4_dpll_regm4xen_xxx()
functions are only applicable to the ABE DPLL and not the other non-core
DPLLs. Therefore, add a new function table for non-core DPLLs that do
not include the 4X-multiplier (M4X).
Please note that using these omap4_dpll_regm4x_xxx() function works for
the non-M4X DPLLs today because we only check to see if the 4X
multiplier is enabled when calculating the rate. However, it is planned
that the dpll functions will be enhanced to enable the 4X multiplier as
necessary (in order to achieve the requested rate) and so calling these
functions for non-M4X dplls will no longer work.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Commit "ARM: dts: OMAP4: Update timer addresses" updated the device-tree
names of the OMAP4 timers 5-7 because the default address for the timers
was changed from the L3 address to the MPU private address. When booting
with device-tree, this introduces a regression when attempting to set
the parent clock of timers 5-7 to the sys_clk_div_ck. Therefore, update
the clock aliases for timer 5-7 to reflect the updated device-tree name
for the timers.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: updated to apply after the CCF conversion]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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There is several different SoCs sharing the sun5i codename: A10s, A12
and A13. Since there is enough differences to not consider those the
same SoCs, change a bit the naming scheme to reflect this.
Moreover, some boards like the olinuxino come in A10s and A13 variants,
which also share the same SoC codename.
So change the naming scheme to reflect both the codename and the market
name of the SoCs used in the dtsi and in the board files
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Commit db298da2c31e1dcf7c9b7c9cef6217ad3449ebb7
"ARM: nomadik: move platform_data definition"
moved the Ux500-specific musb header from <mach/usb.h>
to <linux/platform_data/usb-musb-ux500.h>
However that makes some board code fail to compile
now:
CC arch/arm/mach-ux500/board-mop500.o
linux/arch/arm/mach-ux500/cpu-db8500.c: In function 'u8500_init_devices':
linux/arch/arm/mach-ux500/cpu-db8500.c:226:2: error: implicit declaration of function 'ux500_add_usb' [-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors
make[3]: *** [arch/arm/mach-ux500/cpu-db8500.o] Error 1
make[3]: *** Waiting for unfinished jobs....
make[2]: *** [arch/arm/mach-ux500] Error 2
make[2]: *** Waiting for unfinished jobs....
So fix this up by adding the proper include file that
appears to have been brought in implicitly one or another
way in the past.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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With recent changes in the kernel, the MMCI and PL011 UART
drivers will autonomously request their pins to be muxed in,
so this machine-specific pin hogging code is just interfering
with the proper mechanism and causing regressions in the v3.8
kernel. Delete it and the problems go away.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into fixes
ARM: tegra: fixes for 3.8
This branch contains a few miscellaneous fixes that have shown up in the
last few weeks.
By Sivaram Nair (2) and Hiroshi Doyu (1)
via Stephen Warren
* tag 'tegra-for-3.8-fixes-for-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
amba: tegra-ahb: Fix warning w/o PM_SLEEP
ARM: tegra: fix comment in dsib clk set_parent
ARM: tegra: select correct parent clk for pll_p
Signed-off-by: Olof Johansson <olof@lixom.net>
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Since the clk framework has already taken necessary locks before calling
into the arch clk ops code, no further locks are needed while setting
the parent of dsib clk. This patch removes a comment that indicated
otherwise, and yet did not take any locks.
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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For Tegra30, pll_p clk's parent is wrongly specified as clk_m instead of
pll_ref in the tegra30_clk_init_table and this is resulting in a
boot-time warning. This patch fixes this by correcting the clk init
table.
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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arch/arm/mach-davinci/board-da850-evm.c: In function 'da850_evm_init':
arch/arm/mach-davinci/board-da850-evm.c:1516:2: error: implicit declaration of function 'sram_get_gen_pool' [-Werror=implicit-function-declaration]
arch/arm/mach-davinci/board-da850-evm.c:1516:31: warning: assignment makes pointer from integer without a cast [enabled by default]
Signed-off-by: Olof Johansson <olof@lixom.net>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
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In file included from arch/arm/mach-exynos/clock-exynos5.c:29:0:
arch/arm/mach-exynos/common.h:28:12: warning: 'exynos_pm_late_initcall' defined but not used [-Wunused-function]
Signed-off-by: Olof Johansson <olof@lixom.net>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
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Pull sparc fixes from David Miller:
"Please pull to get these sparc AES/DES/CAMELLIA crypto bug fixes as
well as an addition of a pte_accessible() define for sparc64 and a
hugetlb fix from Dave Kleikamp."
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
sparc64: Set CRYPTO_TFM_REQ_MAY_SLEEP consistently in CAMELLIA code.
sparc64: Set CRYPTO_TFM_REQ_MAY_SLEEP consistently in DES code.
sparc64: Fix ECB looping constructs in AES code.
sparc64: Set CRYPTO_TFM_REQ_MAY_SLEEP consistently in AES code.
sparc64: Fix AES ctr mode block size.
sparc64: Fix unrolled AES 256-bit key loops.
sparc64: Define pte_accessible()
sparc: huge_ptep_set_* functions need to call set_huge_pte_at()
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We use the FPU and therefore cannot sleep during the crypto
loops.
Signed-off-by: David S. Miller <davem@davemloft.net>
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We use the FPU and therefore cannot sleep during the crypto
loops.
Signed-off-by: David S. Miller <davem@davemloft.net>
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Things works better when you increment the source buffer pointer
properly.
Signed-off-by: David S. Miller <davem@davemloft.net>
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We use the FPU and therefore cannot sleep during the crypto
loops.
Signed-off-by: David S. Miller <davem@davemloft.net>
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Like the generic versions, we need to support a block size
of '1' for CTR mode AES.
This was discovered thanks to all of the new test cases added by
Jussi Kivilinna.
Signed-off-by: David S. Miller <davem@davemloft.net>
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The basic scheme of the block mode assembler is that we start by
enabling the FPU, loading the key into the floating point registers,
then iterate calling the encrypt/decrypt routine for each block.
For the 256-bit key cases, we run short on registers in the unrolled
loops.
So the {ENCRYPT,DECRYPT}_256_2() macros reload the key registers that
get clobbered.
The unrolled macros, {ENCRYPT,DECRYPT}_256(), are not mindful of this.
So if we have a mix of multi-block and single-block calls, the
single-block unrolled 256-bit encrypt/decrypt can run with some
of the key registers clobbered.
Handle this by always explicitly loading those registers before using
the non-unrolled 256-bit macro.
This was discovered thanks to all of the new test cases added by
Jussi Kivilinna.
Signed-off-by: David S. Miller <davem@davemloft.net>
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We can elide flush_tlb_*() calls when _PAGE_VALID is clear
as that is the test used to determine whether or not to
queue up a TLB flush in set_pte_at().
Signed-off-by: David S. Miller <davem@davemloft.net>
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Modifying the huge pte's requires that all the underlying pte's be
modified.
Version 2: added missing flush_tlb_page()
Signed-off-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: sparclinux@vger.kernel.org
Signed-off-by: David S. Miller <davem@davemloft.net>
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Pull Xtensa patchset from Chris Zankel:
"This contains support of device trees, many fixes, and code clean-ups"
* tag 'xtensa-20121218' of git://github.com/czankel/xtensa-linux: (33 commits)
xtensa: don't try to build DTB when OF is disabled
xtensa: set the correct ethernet address for xtfpga
xtensa: clean up files to make them code-style compliant
xtensa: provide endianness macro for sparse
xtensa: fix RASID SR initialization
xtensa: initialize CPENABLE SR when core has one
xtensa: reset all timers on initialization
Use for_each_compatible_node() macro.
xtensa: add XTFPGA DTS
xtensa: add support for the XTFPGA boards
xtensa: add device trees support
xtensa: add IRQ domains support
xtensa: add U-Boot image support (uImage).
xtensa: clean up boot make rules
xtensa: fix mb and wmb definitions
xtensa: add s32c1i-based spinlock implementations
xtensa: add s32c1i-based bitops implementations
xtensa: add s32c1i-based atomic ops implementations
xtensa: add s32c1i sanity check
xtensa: add trap_set_handler function
...
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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The last byte of the mac address is determined by a DIP switch, so
update the OF property with that address.
Signed-off-by: Chris Zankel <chris@zankel.net>
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Remove heading and trailing spaces, trim trailing lines, and wrap lines
that are longer than 80 characters.
Signed-off-by: Chris Zankel <chris@zankel.net>
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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set_rasid_register accepts new RASID SR value, but ASID_USER_FIRST is
ASID value for the ring 1; RASID value is made by ASID_INSERT macro.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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XCHAL_CP_NUM is defined in variant/tie.h and it is not included by
head.S, leaving CPENABLE register uninitialised. XCHAL_HAVE_CP is
defined in variant/core.h to 1 when core has CPENABLE SR.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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There are XCHAL_NUM_TIMERS, reset them all.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Add common XTFPGA parts as *.dtsi (base board, flash) and DTS for LX60
and for ML605.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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The Avnet LX60/LX110/LX200 board is an FPGA board that can be configured with
an Xtensa processor and an OpenCores Ethernet device.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Device trees allow specification of hardware topology and device
parameters at runtime instead of hard-coding them in platform setup
code. This allows running single binary kernel on a range of compatible
boards.
New boot parameters tag BP_TAG_FDT is allocated and a pointer to flat
device tree is passed in it.
Note that current interrupt mapping scheme uses single cell for
interrupt identification. That means that IRQ numbers used in DTS must
be CPU internal IRQ numbers, not external. It is possible to extend
interrupt identification to two cells, and use second cell to tell
external IRQ numbers form internal. That would allow to use single DTS
on multiple boards with different mapping of external IRQ numbers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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IRQ domains provide a mechanism for conversion of linux IRQ numbers to
hardware IRQ numbers and vice versus. It is used by OpenFirmware for
linking device tree objects to their respective interrupt controllers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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- remove duplicate rules for binary and packed image
- use predefined macros for ld/objcopy/gzip
- remove build-id section from bootable elf image
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Define mb and wmb as memw to force memory barrier.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Add a brief sanity test of S32C1I functionality. This instruction
is needed by the kernel and userland as part of the base ABI
(including GCC atomic builtins, certain threading packages, future
atomic support in the C++ standard, etc). However, correct operation
of this instruction requires some cooperation by hardware external to
the processor (such as bus bridge, bus fabric, or memory controller).
Minimally exercising this mechanism and reporting explicit status
early in the boot process is helpful to chip vendors using the Linux
kernel as a benchmark of correctness of hardware.
As it turns out, S32C1I is not exercised by the kernel and by uClibc
based userland as of early June 2008. This is expected to change
soon as both incorporate more recent open source developments.
Signed-off-by: Marc Gauthier <marc@tensilica.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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trap_set_handler sets new C-handler in the exception table and returns
previous handler.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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In order to use S32C1I instruction on cores with ATOMCTL SR the register
must be properly initialized.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Although scompare1 may be saved/restored by xchal_ncp_{load,store}
macros, explicit save/restore of registers manipulated by the kernel
itself is considered more correct.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
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